== Series Details == Series: drm/i915: per context slice/subslice powergating (rev5) URL : https://patchwork.freedesktop.org/series/42285/ State : warning == Summary == $ dim checkpatch origin/drm-tip 377ebb5122c5 drm/i915: Program RPCS for Broadwell f8abc1461d28 drm/i915: Record the sseu configuration per-context & engine -:65: ERROR:TRAILING_WHITESPACE: trailing whitespace #65: FILE: drivers/gpu/drm/i915/i915_gem_context.h:161: +^I^I$ total: 1 errors, 0 warnings, 0 checks, 123 lines checked a6a8c598a410 drm/i915/perf: simplify configure all context function 59f0b58443a7 drm/i915/perf: reuse intel_lrc ctx regs macro 2bfb63f77f52 drm/i915/perf: lock powergating configuration to default when active 14eb252b3b42 drm/i915: Expose RPCS (SSEU) configuration to userspace -:40: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #40: v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel) total: 0 errors, 1 warnings, 0 checks, 437 lines checked 92c303df8706 drm/i915: add a sysfs entry to let users set sseu configs _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
