Quoting Chris Wilson (2018-05-09 15:28:00) > Continuing the theme of bypassing ksoftirqd latency, also first try to > directly submit from the CS interrupt handler to clear the ELSP and > queue the next. > > In the past, we have been hesitant to do this as the context switch > processing has been quite heavy, requiring forcewaked mmio. However, as > we now can read the GPU state from the cacheable HWSP, it is relatively > cheap! > > v2: Explain why we test_bit(IRQ_EXECLIST) after doing notify_ring (it's > because the notify_ring() may itself trigger direct submission clearing > the bit) > > Suggested-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> Tvrtko has some extra tests for igt/gem_exec_latency that show the impact of triggering ksoftirqd has on submission latency. It's not pretty. Fortunately, this pair of patches makes a huge difference. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
