Quoting Chris Wilson (2018-05-08 17:30:41) > We assume that the CSB is written using the normal ringbuffer > coherency protocols, as outlined in kernel/events/ring_buffer.c: > > * (HW) (DRIVER) > * > * if (LOAD ->data_tail) { LOAD ->data_head > * (A) smp_rmb() (C) > * STORE $data LOAD $data > * smp_wmb() (B) smp_mb() (D) > * STORE ->data_head STORE ->data_tail > * } > > So we assume that the HW fulfils its ordering requirements (B), and so > we should use a complimentary rmb (C) to ensure that our read of its > WRITE pointer is completed before we start accessing the data. > > The final mb (D) is implied by the uncached mmio we perform to inform > the HW of our READ pointer. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=105064 -References: https://bugs.freedesktop.org/show_bug.cgi?id=105064 Resolved as ba74cb10c775 ("drm/i915/execlists: Delay writing to ELSP until HW has processed the previous write") So the other possibility is that this fixes up the issue with VT-d latency. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx