Quoting Mika Kuoppala (2018-05-08 13:03:13) > Not all architectures guarantee that uncached read will > flush the write combining buffer. So marking it explicitly > is recommended [1]. > > However we know the architecture we are operating on > and can avoid wmb as the UC store will flush the wcb [2]. > > Omit the wmb() before invalidate as redudant. > > v2: squash combining and removal (Chris) > > References: http://yarchive.net/comp/linux/write_combining.html [1] > References: http://download.intel.com/design/PentiumII/applnots/24442201.pdf [2] > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Matthew Auld <matthew.auld@xxxxxxxxx> > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index c879bfd9294f..2126358761a5 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -110,7 +110,8 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma); > > static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv) > { > - /* Note that as an uncached mmio write, this should flush the > + /* > + * Note that as an uncached mmio write, this will flush the > * WCB of the writes into the GGTT before it triggers the invalidate. > */ > I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); > @@ -2418,8 +2419,6 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, > for_each_sgt_dma(addr, sgt_iter, vma->pages) > gen8_set_pte(gtt_entries++, pte_encode | addr); > > - wmb(); > - > /* This next bit makes the above posting read even more important. We Yeah, we should rewrite this comment as well; just skip the first obsolete sentence. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
