On Thu, Apr 05, 2018 at 02:47:56PM +0530, Mahesh Kumar wrote:
> Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
> 11 bits. This patch make changes to use proper mask for ICL+ during
> hardware ddb value readout.
>
> Changes since V1:
> - Use _MASK & _SHIFT macro (James)
> Changes since V2:
> - use kernel type u8 instead of uint8_t
Paulo warned me that I reviewed the wrong one.
rv-b stays with this change.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++----
> 2 files changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 176dca6554f4..e3a6c535617d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6459,6 +6459,9 @@ enum {
>
> #define _PLANE_BUF_CFG_1_B 0x7127c
> #define _PLANE_BUF_CFG_2_B 0x7137c
> +#define SKL_DDB_ENTRY_MASK 0x3FF
> +#define ICL_DDB_ENTRY_MASK 0x7FF
> +#define DDB_ENTRY_END_SHIFT 16
> #define _PLANE_BUF_CFG_1(pipe) \
> _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> #define _PLANE_BUF_CFG_2(pipe) \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 615a084736f3..f7522b268494 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3864,10 +3864,18 @@ static unsigned int skl_cursor_allocation(int num_active)
> return 8;
> }
>
> -static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
> +static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> + struct skl_ddb_entry *entry, u32 reg)
> {
> - entry->start = reg & 0x3ff;
> - entry->end = (reg >> 16) & 0x3ff;
> + u16 mask;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + mask = ICL_DDB_ENTRY_MASK;
> + else
> + mask = SKL_DDB_ENTRY_MASK;
> + entry->start = reg & mask;
> + entry->end = (reg >> DDB_ENTRY_END_SHIFT) & mask;
> +
> if (entry->end)
> entry->end += 1;
> }
> @@ -3898,7 +3906,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> else
> val = I915_READ(CUR_BUF_CFG(pipe));
>
> - skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
> + skl_ddb_entry_init_from_hw(dev_priv,
> + &ddb->plane[pipe][plane_id],
> + val);
> }
>
> intel_display_power_put(dev_priv, power_domain);
> --
> 2.16.2
>
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