On 04/20/2018 01:53 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:49:45PM -0700, Oscar Mateo wrote:
On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
Disable GWL clock gating to prevent two different issues that
might cause hangs.
Please notice that one of the issues is pre-production only.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
Signed-off-by: Oscar Mateo <oscar.mateo@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 50d5507..2c792d7 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -751,6 +751,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
(I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
MSCUNIT_CLKGATE_DIS));
+
+ /* Wa_1406680159:icl */
+ /* Wa_2201832410:icl (pre-prod, only until C0) */
what about adding the REVID checks?
but, well, why one is pre-prod and other is forever?
That's the thing: this is the same workaround for two different HW problems.
One is fixed post-C0, but the other is not, so I cannot add REVID checks :(
Oh of course... Makes sense. Thanks ;)
Good news: Wa_2201832410 has been officially merged with Wa_1406680159,
so I can remove the confusing comment \o/
+ I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+ (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+ GWUNIT_CLKGATE_DIS));
}
void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
--
1.9.1
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