From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Some customers want to know how much of the GPU time are their clients
using in order to make dynamic load balancing decisions.
With the accounting infrastructure in place in the previous patch, we add
a new context param (I915_CONTEXT_GET_ENGINES_BUSY) which points to struct
drm_i915_context_engines_busy, followed by a variable number of structs
drm_i915_context_engine_busy.
Userspace needs to provide the number of attached structures in the
num_engines fields, as well as set args->size to byte size of the provided
buffer.
Attached drm_i915_context_engine_busy objects need to have the class and
instance of the engine which userspace wants to query busyness of
initialized.
Kernel will then report accumulated engine busyness as monotonically
increasing number of nano-seconds the engine spent executing jobs
belonging to this context.
v2:
* Use intel_context_engine_get_busy_time.
* Refactor to only use struct_mutex while initially enabling engine
stats.
v3:
* Fix stats enabling.
v4:
* Change uAPI to enable querying multiple engines at a time.
(Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Cc: gordon.kelly@xxxxxxxxx
---
This version has been compile tested only until acceptable to
everyone.
---
drivers/gpu/drm/i915/i915_gem_context.c | 97 ++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_gem_context.h | 1 +
include/uapi/drm/i915_drm.h | 21 +++++++
3 files changed, 116 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index e9b0940ce7f9..7cfec17b51cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -126,6 +126,9 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
for (i = 0; i < I915_NUM_ENGINES; i++) {
struct intel_context *ce = &ctx->engine[i];
+ if (ctx->i915->engine[i] && ce->stats.enabled)
+ intel_disable_engine_stats(ctx->i915->engine[i]);
+
if (!ce->state)
continue;
@@ -730,11 +733,95 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
return 0;
}
+static int
+get_engines_busy(struct drm_i915_private *i915,
+ struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+ struct drm_i915_context_engine_busy __user *busy_user;
+ struct drm_i915_context_engines_busy engines;
+ struct drm_i915_context_engine_busy busy;
+ bool mutex = false;
+ unsigned int i;
+ int ret = 0;
+
+ if (args->size < sizeof(engines))
+ return -EINVAL;
+
+ if (copy_from_user(&engines, u64_to_user_ptr(args->value),
+ sizeof(engines)))
+ return -EFAULT;
+
+ if (engines.pad || engines.mbz)
+ return -EINVAL;
+
+ if (engines.num_engines == 0 || engines.num_engines > I915_NUM_ENGINES)
+ return -EINVAL;
+
+ if (!access_ok(VERIFY_WRITE, args->value,
+ sizeof(engines) + engines.num_engines * sizeof(busy)))
+ return -EFAULT;
+
+ busy_user = (struct drm_i915_context_engine_busy __user *)
+ ((char __user *)args->value + sizeof(engines));
+
+ for (i = 0; i < engines.num_engines; i++, busy_user++) {
+ struct intel_engine_cs *engine;
+ struct intel_context *ce;
+
+ __copy_from_user(busy_user, &busy, sizeof(busy));
+
+ if (busy.mbz || busy.flags || busy.busy) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ engine = intel_engine_lookup_user(i915,
+ busy.class, busy.instance);
+ if (!engine) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* Enable stats on first query. */
+ ce = &ctx->engine[engine->id];
+ if (!READ_ONCE(ce->stats.enabled)) {
+ /* Grab mutex if need to enable engine stats. */
+ if (!mutex) {
+ ret = i915_mutex_lock_interruptible(&i915->drm);
+ if (!ret)
+ break;
+ mutex = true;
+ }
+
+ if (!ce->stats.enabled) {
+ ret = intel_enable_engine_stats(engine);
+ if (!ret)
+ goto out;
+ ce->stats.enabled = true;
+ }
+ }
+
+ busy.busy =
+ ktime_to_ns(intel_context_engine_get_busy_time(ctx,
+ engine));
+
+ __copy_to_user(busy_user, &busy, sizeof(busy));
+ }
+
+out:
+ if (mutex)
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ return ret;
+}
+
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_file_private *file_priv = file->driver_priv;
struct drm_i915_gem_context_param *args = data;
+ struct drm_i915_private *i915 = to_i915(dev);
struct i915_gem_context *ctx;
int ret = 0;
@@ -753,10 +840,10 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
case I915_CONTEXT_PARAM_GTT_SIZE:
if (ctx->ppgtt)
args->value = ctx->ppgtt->base.total;
- else if (to_i915(dev)->mm.aliasing_ppgtt)
- args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
+ else if (i915->mm.aliasing_ppgtt)
+ args->value = i915->mm.aliasing_ppgtt->base.total;
else
- args->value = to_i915(dev)->ggtt.base.total;
+ args->value = i915->ggtt.base.total;
break;
case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
args->value = i915_gem_context_no_error_capture(ctx);
@@ -767,6 +854,9 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
case I915_CONTEXT_PARAM_PRIORITY:
args->value = ctx->priority;
break;
+ case I915_CONTEXT_GET_ENGINES_BUSY:
+ ret = get_engines_busy(i915, ctx, args);
+ break;
default:
ret = -EINVAL;
break;
@@ -842,6 +932,7 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
}
break;
+ case I915_CONTEXT_GET_ENGINES_BUSY:
default:
ret = -EINVAL;
break;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h
index 159223c5fc5f..e468c971a7f5 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -163,6 +163,7 @@ struct i915_gem_context {
int pin_count;
struct {
seqlock_t lock;
+ bool enabled;
bool active;
ktime_t start;
ktime_t total;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index c82035b71824..c1bdae484594 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1460,6 +1460,26 @@ struct drm_i915_gem_userptr {
__u32 handle;
};
+struct drm_i915_context_engine_busy {
+ __u8 class; /* in/out */
+ __u8 instance; /* in/out */
+
+ __u16 mbz;
+
+ __u32 flags; /* in/out/mbz */
+
+ __u64 busy; /* out/mbz */
+};
+
+struct drm_i915_context_engines_busy {
+ __u32 num_engines; /* in */
+ __u32 pad; /* mbz */
+
+ __u64 mbz;
+
+ struct drm_i915_context_engine_busy engines[0];
+};
+
struct drm_i915_gem_context_param {
__u32 ctx_id;
__u32 size;
@@ -1473,6 +1493,7 @@ struct drm_i915_gem_context_param {
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
#define I915_CONTEXT_DEFAULT_PRIORITY 0
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
+#define I915_CONTEXT_GET_ENGINES_BUSY 0x7
__u64 value;
};
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
