Op 09-04-18 om 21:48 schreef Rodrigo Vivi: > On Wed, Mar 28, 2018 at 06:20:26PM +0200, Maarten Lankhorst wrote: >> Op 28-03-18 om 12:21 schreef Jani Nikula: >>> On Wed, 28 Mar 2018, Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> wrote: >>>> Adding a i915_fifo_underrun_reset debugfs file will make it possible >>>> for IGT tests to clear FIFO underrun fallout at the start of each >>>> subtest, and make re-enable FBC so tests always have maximum exposure >>>> to features used by IGT. FIFO underruns and FBC bugs will no longer >>>> hide when an earlier subtests disables both. >>>> >>>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> >>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105685 >>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105681 >>> FWIW, ack on the idea, didn't look at the implementation. >> Well I had a NV12 test that produced FIFO underruns, did some quick testing against the i915_fifo_underrun_reset file and manually writing it does reset FIFO underruns. >> Immediately after i915_fbc_status still reads "FBC disabled: underrun detected", but this is cleared by the next atomic commit. So I think it works, and can be used for igt in the way I wrote it. > What about a error message change on fbc_status to reflect this temporary state? > Just to avoid later confusion on expectation. Done, if an underrun is cleared, the reason will be set to 'FIFO underrun cleared'. > But the approach and code look sane for me, so anyways: > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> Thanks for reviewing, pushed. :) _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
