On Fri, Apr 06, 2018 at 12:28:30PM -0700, Dhinakaran Pandiyan wrote:
>
>
>
> On Fri, 2018-04-06 at 14:52 -0400, Lyude Paul wrote:
> > When doing a modeset where the sink is transitioning from D3 to D0 , it
> > would sometimes be possible for the initial power_up_phy() to start
> > timing out. This would only be observed in the last action before the
> > sink went into D3 mode was intel_dp_sink_dpms(DRM_MODE_DPMS_OFF). We
> > originally thought this might be an issue with us accidentally shutting
> > off the aux block when putting the sink into D3, but since the DP spec
> > mandates that sinks must wake up within 1ms while we have 100ms to
> > respond to an ESI irq, this didn't really add up. Turns out that the
> > problem is more subtle then that:
> >
> > It turns out that the timeout is from us not enabling DPMS on the MST
> > hub before actually trying to initiate sideband communications. This
> > would cause the first sideband communication (power_up_phy()), to start
> > timing out because the sink wasn't ready to respond. Afterwards, we
> > would call intel_dp_sink_dpms(DRM_MODE_DPMS_ON) in
> > intel_ddi_pre_enable_dp(), which would actually result in waking up the
> > sink so that sideband requests would work again.
> >
> > Since DPMS is what lets us actually bring the hub up into a state where
> > sideband communications become functional again, we just need to make
> > sure to enable DPMS on the display before attempting to perform sideband
> > communications.
> >
>
> Matches my understanding of the problem
>
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
>
> It's better to get an ack from Ville considering I was okay with the
> D3_AUX_ON solution too.
lgtm
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
>
> > Changes since v1:
> > - Remove comment above if (!intel_dp->is_mst) - vsryjala
> > - Move intel_dp_sink_dpms() for MST into intel_dp_post_disable_mst() to
> > keep enable/disable paths symmetrical
> > - Improve commit message - dhnkrn
> > Changes since v2:
> > - Only send DPMS off when we're disabling the last sink, and only send
> > DPMS on when we're enabling the first sink - dhnkrn
> > Changes since v3:
> > - Check against is_mst, not intel_dp->is_mst - dhnkrn/vsyrjala
> >
> > Signed-off-by: Lyude Paul <lyude@xxxxxxxxxx>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Cc: Laura Abbott <labbott@xxxxxxxxxx>
> > Cc: stable@xxxxxxxxxxxxxxx
> > Fixes: ad260ab32a4d9 ("drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.")
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++--
> > drivers/gpu/drm/i915/intel_dp_mst.c | 8 +++++++-
> > 2 files changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index a6672a9abd85..92cb26b18a9b 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2324,7 +2324,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> > intel_prepare_dp_ddi_buffers(encoder, crtc_state);
> >
> > intel_ddi_init_dp_buf_reg(encoder);
> > - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > + if (!is_mst)
> > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > intel_dp_start_link_train(intel_dp);
> > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> > intel_dp_stop_link_train(intel_dp);
> > @@ -2422,12 +2423,15 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> > struct intel_dp *intel_dp = &dig_port->dp;
> > + bool is_mst = intel_crtc_has_type(old_crtc_state,
> > + INTEL_OUTPUT_DP_MST);
> >
> > /*
> > * Power down sink before disabling the port, otherwise we end
> > * up getting interrupts from the sink on detecting link loss.
> > */
> > - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > + if (!is_mst)
> > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> >
> > intel_disable_ddi_buf(encoder);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> > index c3de0918ee13..9e6956c08688 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > @@ -180,9 +180,11 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,
> > intel_dp->active_mst_links--;
> >
> > intel_mst->connector = NULL;
> > - if (intel_dp->active_mst_links == 0)
> > + if (intel_dp->active_mst_links == 0) {
> > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > intel_dig_port->base.post_disable(&intel_dig_port->base,
> > old_crtc_state, NULL);
> > + }
> >
> > DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
> > }
> > @@ -223,7 +225,11 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
> >
> > DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
> >
> > + if (intel_dp->active_mst_links == 0)
> > + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> > +
> > drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
> > +
> > if (intel_dp->active_mst_links == 0)
> > intel_dig_port->base.pre_enable(&intel_dig_port->base,
> > pipe_config, NULL);
--
Ville Syrjälä
Intel OTC
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