Hi 2012/8/9 Daniel Vetter <daniel at ffwll.ch>: > On Thu, Aug 09, 2012 at 12:55:41PM +0300, Jani Nikula wrote: >> On Wed, 08 Aug 2012, Paulo Zanoni <przanoni at gmail.com> wrote: >> > From: Paulo Zanoni <paulo.r.zanoni at intel.com> >> > >> > Correctly erase the values previously set and also check for 6pbc and >> > 10bpc. >> >> 6 *bpc*. But is the 6 or 10 bpc usage below correct anyway, as the spec >> says they are not supported by HDMI or DVI? (Either way, the erase part >> of the patch is valid.) > > Iirc the intel_crtc->bpp computation should take these constraints into > account. On a quick look intel_choose_pipe_bpp_dither seems to dtrt. Yes, that's exactly what I was checking right now... Also, a quick check on the HDMI spec shows that is does support 30bpp, so 10bpc might be allowed... I really think that inside encoder_mode_set we really shouldn't be doing failure checks anymore since we can't fail and return error codes. Also, my evil plans include using this code for DP too, that's why I covered all cases. Still, I did some checks with testdisplay and it seems our non-24-bpp Kernel code could use some love. > -Daniel > > -- > Daniel Vetter > Mail: daniel at ffwll.ch > Mobile: +41 (0)79 365 57 48 -- Paulo Zanoni
