From: Paulo Zanoni <paulo.r.zanoni at intel.com> HDMI already works fine on Haswell, but we still have room for improvements. This series will make us less dependent on the bits set by the BIOS, will fix cases where DVI was not working and will also improve the cases where we have 2 HDMI monitors. - Patches 1-4 are all about the DDI_FUNC_CTL register. - Patch 5 is to satisfy my OCD. - Patch 6 was spotted while writing patch 5. - Patches 7-8 are about setting PLLs. Paulo Zanoni (8): drm/i915: fix pipe DDI mode select drm/i915: set the DDI sync polarity bits drm/i915: correctly set the DDI_FUNC_CTL bpc field drm/i915: completely reset the value of DDI_FUNC_CTL drm/i915: reindent Haswell register definitions drm/i915: add parentheses around PIXCLK_GATE definitions drm/i915: try harder to find WR PLL clock settings drm/i915: try to use WR PLL 2 drivers/gpu/drm/i915/i915_reg.h | 184 ++++++++++++++++++--------------------- drivers/gpu/drm/i915/intel_ddi.c | 108 ++++++++++++++++------- 2 files changed, 163 insertions(+), 129 deletions(-) -- 1.7.11.2
