On Mon, Apr 02, 2018 at 05:20:22PM +0530, Ramalingam C wrote: > As per DP spec when R0 mismatch is detected, HDCP source supported > re-read the R0 atleast twice. > > And For HDMI and DP minimum wait required for the R0 availability is > 100mSec. So this patch changes the wait time to 100mSec but retries > twice with the time interval of 100mSec for each attempt. > > This patch is needed for DP HDCP1.4 CTS Test: 1A-06. > > v2: > No Change > v3: > Comment on R0 retry is moved closer to the code[Seanpaul] > v4: > Removing unwanted noise introduced in v3. > > Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx> Reviewed-by: Sean Paul <seanpaul@xxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_hdcp.c | 27 +++++++++++++++++++-------- > 1 file changed, 19 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c > index 14ca5d3057a7..f2cf2e3acd3c 100644 > --- a/drivers/gpu/drm/i915/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/intel_hdcp.c > @@ -506,15 +506,26 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port, > */ > wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); > > - ri.reg = 0; > - ret = shim->read_ri_prime(intel_dig_port, ri.shim); > - if (ret) > - return ret; > - I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); > + tries = 3; > > - /* Wait for Ri prime match */ > - if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & > - (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { > + /* > + * DP HDCP Spec mandates the two more reattempt to read R0, incase > + * of R0 mismatch. > + */ > + for (i = 0; i < tries; i++) { > + ri.reg = 0; > + ret = shim->read_ri_prime(intel_dig_port, ri.shim); > + if (ret) > + return ret; > + I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); > + > + /* Wait for Ri prime match */ > + if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) & > + (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) > + break; > + } > + > + if (i == tries) { > DRM_ERROR("Timed out waiting for Ri prime match (%x)\n", > I915_READ(PORT_HDCP_STATUS(port))); > return -ETIMEDOUT; > -- > 2.7.4 > -- Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx