> -----Original Message----- > From: Maarten Lankhorst [mailto:maarten.lankhorst@xxxxxxxxxxxxxxx] > Sent: Thursday, March 29, 2018 2:19 PM > To: Srinivas, Vidya <vidya.srinivas@xxxxxxxxx>; intel- > gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: Re: [PATCH v18 18/18] drm/i915: Keep plane size mult of > 4 for NV12 > > Op 29-03-18 om 10:06 schreef Vidya Srinivas: > > As per display WA 1106, to avoid corruption issues > > NV12 plane height needs to be multiplier of 4 Hence we modify the fb > > src and destination height and width to be multiples of 4. Without > > this, pipe fifo underruns were seen on APL and KBL. > > > > Credits-to: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> > > Signed-off-by: Vidya Srinivas <vidya.srinivas@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/intel_drv.h | 2 ++ > > drivers/gpu/drm/i915/intel_sprite.c | 8 ++++++++ > > 2 files changed, 10 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h > > b/drivers/gpu/drm/i915/intel_drv.h > > index 9c58da0..a1f718d 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -159,6 +159,8 @@ > > #define INTEL_I2C_BUS_DVO 1 > > #define INTEL_I2C_BUS_SDVO 2 > > > > +#define MULT4(x) ((x + 3) & ~0x03) > > + > > /* these are outputs from the chip - integrated only > > external chips are via DVO or SDVO output */ enum > > intel_output_type { diff --git a/drivers/gpu/drm/i915/intel_sprite.c > > b/drivers/gpu/drm/i915/intel_sprite.c > > index 538d938..9f466c6 100644 > > --- a/drivers/gpu/drm/i915/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/intel_sprite.c > > @@ -261,6 +261,14 @@ skl_update_plane(struct intel_plane *plane, > > crtc_w--; > > crtc_h--; > > > > + if (fb->format->format == DRM_FORMAT_NV12) { > > + src_w = MULT4(src_w); > > + src_h = MULT4(src_h); > > + crtc_w = MULT4(crtc_w); > > + crtc_h = MULT4(crtc_h); > > + DRM_ERROR("%d %d %d %d\n", src_w, src_h, crtc_w, > crtc_h); > > + } > > + > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); > > > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > > Nearly there! > > Do we have limitations for width too? But I think we shouldn't ever adjust > src for any format. > This means that we should probably get rid of the drm_rect_adjust_size call > in intel_check_sprite_plane. > > If any limitations of NV12 are hit, we should reject with -EINVAL instead so > userspace can decide what to do. > The best place to put those checks is probably in skl_update_scaler, where > they will be checked by the primary plane too. > > This will mean the tests fail, but that can be fixed by selecting 16 as > width/height for NV12 in IGT. If you change it to 16 you can put my r-b on it. > > Also I think we should put the same limitations for width and height being a > multiple in intel_framebuffer_init. > > And on a final note for patch ordering, put the workaround and gen10 patch > before enabling nv12 support. Thank you. I have added the restriction in intel_framebuffer_init and have re-ordered the series. Have also floated the i-g-t patch with 16x16 buffer and I have included your r-b. Kindly have a check. Currently since we have 17x17 the restriction hits and kernel message fb dimensions are not right is seen for tests. If the 16x16 i-g-t patch gets merged, we can get the results. On my side, I have tested with many buffers (mult of 4) and no underruns are seen. https://patchwork.freedesktop.org/series/39670/ (rev 7) > > ~Maarten _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
