== Series Details == Series: series starting with [v2,01/10] drm: Add DP PSR2 sink enable bit URL : https://patchwork.freedesktop.org/series/40702/ State : warning == Summary == $ dim checkpatch origin/drm-tip 38150dd0cc54 drm: Add DP PSR2 sink enable bit b58a3e8a7618 drm: Add DP last received PSR SDP VSC register and bits 99b23cf0dceb drm/i915/psr: Nuke aux frame sync 42e34d55f628 drm/i915/psr: Tie PSR2 support to Y coordinate requirement 3c0441b04e7a drm/i915/psr/cnl: Enable Y-coordinate support in source -:26: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #26: FILE: drivers/gpu/drm/i915/i915_reg.h:4055: +#define EDP_Y_COORDINATE_VALID (1<<26) /* GLK and CNL+ */ ^ -:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #27: FILE: drivers/gpu/drm/i915/i915_reg.h:4056: +#define EDP_Y_COORDINATE_ENABLE (1<<25) /* GLK and CNL+ */ ^ -:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV) #35: FILE: drivers/gpu/drm/i915/i915_reg.h:7063: +#define VSC_DATA_SEL_SOFTWARE_CONTROL (1<<25) /* GLK and CNL+ */ ^ total: 0 errors, 0 warnings, 3 checks, 43 lines checked b758759a05ee drm/i915/psr: Do not override PSR2 sink support 8d70d650ad61 drm/i915/psr: Use PSR2 macro for PSR2 d64ec6a72ea0 drm/i915/psr: Cache sink synchronization latency c7f3ff827a03 drm/i915/psr: Set DPCD PSR2 enable bit when needed d816dbeca7de drm/i915/debugfs: Print sink PSR status _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
