== Series Details == Series: ICL reviewed mergeable patches URL : https://patchwork.freedesktop.org/series/40585/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8689ec52c22b drm/i915/icl: Add register definitions for Combo PHY vswing sequences. a8fa787db803 drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake. 8dda02f88963 drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI -:37: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0p1' - possible side-effects? #37: FILE: drivers/gpu/drm/i915/i915_reg.h:1812: +#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \ + _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) total: 0 errors, 0 warnings, 1 checks, 122 lines checked 72ee7a1a485c drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer 984e455fd5ea drm/i915/icl: HPD pin for port F 79f23d6f9352 drm/i915/icl: Added 5k source scaling support for Gen11 platform 7960f70290b5 drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
