On Thu, Mar 22, 2018 at 02:48:47PM -0700, José Roberto de Souza wrote:
> This will be helpful to debug what hardware is actually tracking.
>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 47 +++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++
> 2 files changed, 65 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 0a0642c61cd0..3182e9a7cc5d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2641,6 +2641,43 @@ static void psr_sink_last_received_psr_sdp_sprintf(struct seq_file *m, u32 val)
> seq_puts(m, "\tY-Coordinate valid\n");
> }
>
> +static void psr_event_exit_sprintf(struct seq_file *m, u32 val,
> + bool psr2_enabled)
> +{
> + if (val & EDP_PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
> + seq_puts(m, "\tPSR2 watchdog timer expired\n");
> + if ((val & EDP_PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
> + seq_puts(m, "\tPSR2 disabled\n");
> + if (val & EDP_PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
> + seq_puts(m, "\tSU dirty FIFO underrun\n");
> + if (val & EDP_PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
> + seq_puts(m, "\tSU CRC FIFO underrun\n");
> + if (val & EDP_PSR_EVENT_GRAPHICS_RESET)
> + seq_puts(m, "\tGraphics reset\n");
> + if (val & EDP_PSR_EVENT_PCH_INTERRUPT)
> + seq_puts(m, "\tPCH interrupt\n");
> + if (val & EDP_PSR_EVENT_MEMORY_UP)
> + seq_puts(m, "\tMemory up\n");
> + if (val & EDP_PSR_EVENT_FRONT_BUFFER_MODIFY)
> + seq_puts(m, "\tFront buffer modification\n");
> + if (val & EDP_PSR_EVENT_WD_TIMER_EXPIRE)
> + seq_puts(m, "\tPSR watchdog timer expired\n");
> + if (val & EDP_PSR_EVENT_PIPE_REGISTERS_UPDATE)
> + seq_puts(m, "\tPIPE registers updated\n");
> + if (val & EDP_PSR_EVENT_REGISTER_UPDATE)
> + seq_puts(m, "\tRegister update\n");
> + if (val & EDP_PSR_EVENT_HDCP_ENABLE)
> + seq_puts(m, "\tHDCP enabled\n");
> + if (val & EDP_PSR_EVENT_KVMR_SESSION_ENABLE)
> + seq_puts(m, "\tKVMR session enabled\n");
> + if (val & EDP_PSR_EVENT_VBI_ENABLE)
> + seq_puts(m, "\tVBI enabled\n");
> + if (val & EDP_PSR_EVENT_LPSP_MODE_EXIT)
> + seq_puts(m, "\tLPSP mode exited\n");
> + if ((val & EDP_PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
> + seq_puts(m, "\tPSR disabled\n");
> +}
> +
> static int i915_edp_psr_status(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -2716,6 +2753,16 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>
> seq_printf(m, "Performance_Counter: %u\n", psrperf);
> }
> +
> + if (INTEL_GEN(dev_priv) >= 9) {
> + u32 val = I915_READ(EDP_PSR_EVENT);
What I'm afraid here is that this really shows the last event or the first one after we cleared.
> +
> + seq_printf(m, "Event triggered PSR exit: 0x%x\n", val);
> + psr_event_exit_sprintf(m, val, dev_priv->psr.psr2_enabled);
> + /* clean events */
> + I915_WRITE(EDP_PSR_EVENT, val);
And to clear do we really need to set the bits or clear the bits?
> + }
> +
> if (dev_priv->psr.psr2_enabled) {
> u32 psr2 = I915_READ(EDP_PSR2_STATUS);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e660c8a707cf..45f7703a9ee6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3907,6 +3907,24 @@ enum {
> #define EDP_PSR2_IDLE_FRAME_MASK 0xf
> #define EDP_PSR2_IDLE_FRAME_SHIFT 0
>
> +#define EDP_PSR_EVENT _MMIO(0x6f848)
> +#define EDP_PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17)
> +#define EDP_PSR_EVENT_PSR2_DISABLED (1 << 16)
> +#define EDP_PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15)
> +#define EDP_PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14)
> +#define EDP_PSR_EVENT_GRAPHICS_RESET (1 << 12)
> +#define EDP_PSR_EVENT_PCH_INTERRUPT (1 << 11)
> +#define EDP_PSR_EVENT_MEMORY_UP (1 << 10)
> +#define EDP_PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9)
> +#define EDP_PSR_EVENT_WD_TIMER_EXPIRE (1 << 8)
> +#define EDP_PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6)
> +#define EDP_PSR_EVENT_REGISTER_UPDATE (1 << 5)
> +#define EDP_PSR_EVENT_HDCP_ENABLE (1 << 4)
> +#define EDP_PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3)
> +#define EDP_PSR_EVENT_VBI_ENABLE (1 << 2)
> +#define EDP_PSR_EVENT_LPSP_MODE_EXIT (1 << 1)
> +#define EDP_PSR_EVENT_PSR_DISABLE (1 << 0)
> +
> #define EDP_PSR2_STATUS _MMIO(0x6f940)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> #define EDP_PSR2_STATUS_STATE_SHIFT 28
> --
> 2.16.2
>
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