We do end up setting ring frequencies on a hardware
which is not yet there wrt runtime pm enablement.
Instead of ending up in an endless loop iterating through
frequencies if min and max frequencies are still set to zero,
warn and bail out early.
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dd5ddb77b306..61378222f4dd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6918,6 +6918,11 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
/* convert DDR frequency from units of 266.6MHz to bandwidth */
min_ring_freq = mult_frac(min_ring_freq, 8, 3);
+ if (WARN_ON(rps->min_freq == 0 ||
+ rps->max_freq == 0 ||
+ min_ring_freq == 0))
+ return;
+
min_gpu_freq = rps->min_freq;
max_gpu_freq = rps->max_freq;
if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
--
2.14.1
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