Quoting Yunwei Zhang (2018-03-19 21:50:07) > WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO > read into Slice/Subslice specific registers, MCR packet control > register(0xFDC) needs to be programmed to point to any enabled > slice/subslice pair. Otherwise, incorrect value will be returned. > > However, that means each subsequent MMIO read will be forwarded to a > specific slice/subslice combination as read is unicast. This is OK since > slice/subslice specific register values are consistent in almost all cases > across slice/subslice. There are rare occasions such as INSTDONE that this > value will be dependent on slice/subslice combo, in such cases, we need to > program 0xFDC and recover this after. This is already covered by > read_subslice_reg for INSTDONE. > > Also, 0xFDC will lose its information after TDR/engine reset/power state > change. > > Signed-off-by: Yunwei Zhang <yunwei.zhang@xxxxxxxxx> > Cc: Oscar Mateo <oscar.mateo@xxxxxxxxx> > Cc: Michel Thierry <michel.thierry@xxxxxxxxx> > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_engine_cs.c | 43 ++++++++++++++++++++++++++++++++-- > 1 file changed, 41 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index a2b1e9e..bc8fed7 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -781,6 +781,29 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type) > } > } > > +static u32 calculate_mcr(u32 mcr, struct drm_i915_private *dev_priv) > +{ > + const struct sseu_dev_info *sseu = &(INTEL_INFO(dev_priv)->sseu); INTEL_SSEU(dev_priv); > + u32 slice = find_last_bit((unsigned long *)&(sseu->slice_mask), > + sizeof(sseu->slice_mask)); > + u32 subslice = find_last_bit((unsigned long *)&(sseu->subslice_mask[slice]), > + sizeof(sseu->subslice_mask[0])); You seem to have mispelt fls(). Or send a patch to convert find_last_bit() into fls() for known small sizes. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx