Failed to receive this mail for 5/6 patch (couldn't find it in my
mailbox). So pasted the comments from patchwork. Thanks for the comments!Quoting Jackie Li (2018-03-02 02:16:45) > +++ b/drivers/gpu/drm/i915/intel_wopcm.c > @@ -219,3 +219,67 @@ int intel_wopcm_init(struct intel_wopcm *wopcm) > > return 0; > } > + > +static inline int write_and_verify(struct drm_i915_private *dev_priv, > + i915_reg_t reg, u32 val, u32 mask, > + u32 locked_bit) > +{ > + u32 reg_val; > + > + GEM_BUG_ON(val & ~mask); > + > + I915_WRITE(reg, val); > + > + reg_val = I915_READ(reg); I guess I would have expected the error message here, with the wanted value vs. what was in the register. <SNIP> > +err_out: > + DRM_ERROR("Failed to init WOPCM registers:\n"); > + DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n", > + I915_READ(DMA_GUC_WOPCM_OFFSET)); > + DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE)); As this doesn't really give information what were the computed write values. But if you see this is most useful for debuggin, this is; This is for debugging. and the consideration was to print both the offset and size register values for any reg update errors, the calculated values were printed as debug messages during wopcm partitioning (wopcm_init) Regards, -Jackie
|
_______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx