On Fri, 2018-03-09 at 14:05 +0200, Jani Nikula wrote: > On Thu, 08 Mar 2018, matthew.s.atwood@xxxxxxxxx wrote: > > > > From: Matt Atwood <matthew.s.atwood@xxxxxxxxx> > > > > Previously it was assumed that eDP panels would advertise the > > lowest link > > rate required for their singular mode to function. With the > > introduction > > of more advanced features there are advantages to a panel > > advertising a > > higher rate then it needs for a its given mode. For panels that > > did, the > > driver previously used a higher rate then necessary for that mode. > > > > Signed-off-by: Matt Atwood <matthew.s.atwood@xxxxxxxxx> > > --- > > drivers/gpu/drm/i915/intel_dp.c | 10 ---------- > > 1 file changed, 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > b/drivers/gpu/drm/i915/intel_dp.c > > index a2eeede..aa6d77d 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -1758,16 +1758,6 @@ intel_dp_compute_config(struct intel_encoder > > *encoder, > > dev_priv->vbt.edp.bpp); > > bpp = dev_priv->vbt.edp.bpp; > > } > > - > > - /* > > - * Use the maximum clock and number of lanes the > > eDP panel > > - * advertizes being capable of. The panels are > > generally > > - * designed to support only a single clock and > > lane > > - * configuration, and typically these values > > correspond to the > > - * native resolution of the panel. > > - */ > > - min_lane_count = max_lane_count; > > - min_clock = max_clock; > Please see my reply to Manasi's identical patch [1]. If we apply this > as-is, it will regress and will be reverted. > > BR, > Jani. > > > [1] http://patchwork.freedesktop.org/patch/msgid/1520579339-14745-1- > git-send-email-manasi.d.navare@xxxxxxxxx to consolidate some of the information the bug that's referenced in Manasi's patch is https://bugs.freedesktop.org/show_bug.cgi?id=73539. I understand this bug as the following some panels may advertise a mode that requires less then MAX_LANE_COUNT, however those panels would fail if less lanes were used. When this bug was filed the compute config inner for loop iterated on rate and the outer iterated on lanes; this is now flipped. It *should* be the case that the lowest frequency with the max amount of lanes is preferred. Given the opposite behavior of the alogorithm to select I dont think we'd come across this again. Even if I'm wrong we could still min_lane_count = max_lane count and let the clock optimize itself. I guess my question is, is there also a bug where if MAX_RATE wasnt used we saw a panel fail as well? Matt > > > > > > } > > > > for (; bpp >= 6*3; bpp -= 2*3) { _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
