Hi Matt, On Tue, Mar 06, 2018 at 10:37:48AM -0800, matthew.s.atwood@xxxxxxxxx wrote: > From: Matt Atwood <matthew.s.atwood@xxxxxxxxx> > > DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheme from 8 > bits to 7 bits in DPCD 0x000e. The 8th bit describes a new feature, for > panels that use this new feature, this would cause a wait interval for > clock recovery of at least 512 ms, much higher then spec maximum of 16 ms. > This behavior is described in table 2-158 of DP 1.4 spec address 0000Eh. > To avoid breaking panels that are not spec compliant we now warn on > invalid values. > > V2: commit title/message, masking all 7 bits, warn on out of spec values. > > Signed-off-by: Matt Atwood <matthew.s.atwood@xxxxxxxxx> Tested-by: Benson Leung <bleung@xxxxxxxxxxxx> Tested this patch on a DP 1.3 panel which sets the EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT bit in DPCD 0000Eh. It has a value of 0x80 in that field, indicating the extended caps, and 400us for the Main-Link Channel Equalization phase. Confirmed that link training passes normally where prior to this it would fail after the driver waits too long. Thanks for the fix! -- Benson Leung Staff Software Engineer Chrome OS Kernel Google Inc. bleung@xxxxxxxxxx Chromium OS Project bleung@xxxxxxxxxxxx
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