Quoting Jackie Li (2018-03-01 01:01:39) > GuC WOPCM registers are write-once registers. Current driver code accesses > these registers without checking the accessibility to these registers which > will lead to unpredictable driver behaviors if these registers were touch > by other components (such as faulty BIOS code). > > This patch moves the GuC WOPCM registers updating code into > intel_guc_wopcm.c and adds check before and after the update to GuC WOPCM > registers so that we can make sure the driver is in a known state before > and after writing to these write-once registers. > > v6: > - Made sure module reloading won't bug the kernel while doing > locking status checking > > v7: > - Fixed patch format issues > > v8: > - Fixed coding style issue on register lock bit macro definition (Sagar) > > v9: > - Avoided to use redundant !! to cast uint to bool (Chris) > - Return error code instead of GEM_BUG_ON for locked with invalid register > values case (Sagar) > - Updated guc_wopcm_hw_init to use guc_wopcm as first parameter (Michal) > - Added code to set and validate the HuC_LOADING_AGENT_GUC bit in GuC > WOPCM offset register based on the presence of HuC firmware (Michal) > - Use bit fields instead of macros for GuC WOPCM flags (Michal) > > v10: > - Refined variable names, removed redundant comments (Joonas) > - Introduced lockable_reg to handle the write once register write and > propagate the write error to caller (Joonas) > - Used lockable_reg abstraction to avoid locking bit check on generic > i915_reg_t (Michal) > - Added log message for error paths (Michal) > - Removed hw_updated flag and only relies on real hardware status > > v11: > - Replaced lockable_reg with simplified function (Michal) > - Used new macros for locking bits of WOPCM size/offset registers instead > of using BIT(0) directly (Michal) > - use intel_wopcm_init_hw() called from intel_gem_init_hw() to do GuC > WOPCM register setup instead of calling from intel_uc_init_hw() (Michal) > > BSpec: 10875, 10833 > > Cc: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> Michal, your turn! Joonas, Sagar and myself did the first 3, so the fourth must be yours for the royal flush ;) -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
