On Wed, 28 Feb 2018, Manasi Navare <manasi.d.navare@xxxxxxxxx> wrote:
> dp_rates[] array is a superset of all the link rates supported
> by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate
> to the set of link rates supported by sink. This patch adds this rate
> to dp_rates[] array that gets used to populate the sink_rates[]
> array limited by max rate obtained from DP_MAX_LINK_RATE DPCD register.
>
> v2:
> * Rebased on top of Jani's localized rates patch
>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
And pushed to dinq, thanks for the patch.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 750c25a..aba2f45 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -136,7 +136,7 @@ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
> {
> static const int dp_rates[] = {
> - 162000, 270000, 540000
> + 162000, 270000, 540000, 810000
> };
> int i, max_rate;
--
Jani Nikula, Intel Open Source Technology Center
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