On Tue, 27 Feb 2018, Manasi Navare <manasi.d.navare@xxxxxxxxx> wrote:
> default_rates[] array is a superset of all the link rates supported
> by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate
> to the set of link rates supported by sink. This patch adds this rate
> to default_rates[] array that gets used to populate the sink_rates[]
> array limited by max rate obtained from DP_MAX_LINK_RATE DPCD register.
>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2a3b3ae..f0766fb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -103,7 +103,7 @@ static const int skl_rates[] = { 162000, 216000, 270000,
> static const int cnl_rates[] = { 162000, 216000, 270000,
> 324000, 432000, 540000,
> 648000, 810000 };
> -static const int default_rates[] = { 162000, 270000, 540000 };
> +static const int default_rates[] = { 162000, 270000, 540000, 810000 };
Now this is part of the reason I wanted to do [1], especially the part
that switches to using hsw_rates and g4x_rates, instead of doing
ARRAY_SIZE(default_rates) - 1. This innocent looking patch now "enables"
HBR2 on g4x and HBR3 on hsw and bdw.
BR,
Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/20180227105911.4485-1-jani.nikula@xxxxxxxxx
>
> /**
> * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
--
Jani Nikula, Intel Open Source Technology Center
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