When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it self, so lets use the mutex register that is available in gen9+ to avoid concurrent access by hardware and driver. Older gen handling will be done separated. Reference: https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol12-display.pdf Page 198 - AUX programming sequence Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_reg.h | 9 ++++++++ drivers/gpu/drm/i915/intel_dp.c | 47 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eea5b2c537d4..f36e839b4b4f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5385,6 +5385,15 @@ enum { #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) +#define _DPA_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6402C) +#define _DPB_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6412C) +#define _DPC_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6422C) +#define _DPD_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6432C) +#define _DPF_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6452C) +#define DP_AUX_CH_MUTEX(port) _MMIO_PORT(port, _DPA_AUX_CH_MUTEX, _DPB_AUX_CH_MUTEX) +#define DP_AUX_CH_MUTEX_ENABLE (1 << 31) +#define DP_AUX_CH_MUTEX_STATUS (1 << 30) + /* * Computing GMCH M and N values for the Display Port link * diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2c3eb90b9499..7004239e4c9e 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1081,6 +1081,42 @@ static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp, aux_clock_divider); } +static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = + to_i915(intel_dig_port->base.base.dev); + + if (INTEL_GEN(dev_priv) < 9) + return true; + + /* Spec says that mutex is acquired when status bit is read as unset, + * here waiting for 2msec(+-4 aux transactions) before give up. + */ + if (intel_wait_for_register(dev_priv, DP_AUX_CH_MUTEX(intel_dp->aux_ch), + DP_AUX_CH_MUTEX_STATUS, 0, 2)) { + DRM_DEBUG_KMS("aux channel %c locked for 2msec, timing out\n", + aux_ch_name(intel_dp->aux_ch)); + return false; + } + + return true; +} + +static void intel_dp_aux_ch_unlock(struct intel_dp *intel_dp) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = + to_i915(intel_dig_port->base.base.dev); + + if (INTEL_GEN(dev_priv) < 9) + return; + + /* set the status bit releases the mutex + keeping mutex enabled */ + I915_WRITE(DP_AUX_CH_MUTEX(intel_dp->aux_ch), + DP_AUX_CH_MUTEX_ENABLE | DP_AUX_CH_MUTEX_STATUS); +} + static int intel_dp_aux_ch(struct intel_dp *intel_dp, const uint8_t *send, int send_bytes, @@ -1119,6 +1155,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, intel_dp_check_edp(intel_dp); + if (!intel_dp_aux_ch_trylock(intel_dp)) { + ret = -EBUSY; + goto out_locked; + } + /* Try to wait for any previous AUX channel activity */ for (try = 0; try < 3; try++) { status = I915_READ_NOTRACE(ch_ctl); @@ -1248,6 +1289,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, ret = recv_bytes; out: + intel_dp_aux_ch_unlock(intel_dp); +out_locked: pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); if (vdd) @@ -1544,6 +1587,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp) else intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; + if (INTEL_GEN(dev_priv) >= 9) + I915_WRITE(DP_AUX_CH_MUTEX(intel_dp->aux_ch), + DP_AUX_CH_MUTEX_ENABLE); + drm_dp_aux_init(&intel_dp->aux); /* Failure to allocate our preferred name is not critical */ -- 2.16.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
