On Tue, 2018-02-13 at 15:26 -0800, Rodrigo Vivi wrote:
> Missing flips when FBC is enabled with PSR
> link off/PSR2 deep sleep scenarios.
>
I am wary of this. Is there a test to compare flip misses before/after
this workaround? We also have to confirm disabling FBC has the same
effect of not having this workaround.
+Ville
+Chris
any idea on how to quantitatively test if this workaround improves
anything?
> WA: When FBC is enabled with PSR/PSR2,
> set bit 30 of MMIO register 0x420CC to 1b.
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 8 +++++++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac09d17cd835..0f423cd52983 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7153,6 +7153,7 @@ enum {
> #define CHICKEN_TRANS_A 0x420c0
> #define CHICKEN_TRANS_B 0x420c4
> #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define DDI_MASK_INTERRUPTS_PSR (1<<30)
> #define DDI_TRAINING_OVERRIDE_ENABLE (1<<19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1<<18)
> #define DDIE_TRAINING_OVERRIDE_ENABLE (1<<17) /* CHICKEN_TRANS_A only */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 49554036ffb8..43c702b70519 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -481,7 +481,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
> struct drm_device *dev = dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - u32 chicken;
> + u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
>
> if (dev_priv->psr.psr2_support) {
> chicken = PSR2_VSC_ENABLE_PROG_HEADER;
> @@ -508,6 +508,12 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
> EDP_PSR_DEBUG_MASK_HPD |
> EDP_PSR_DEBUG_MASK_LPSP);
> }
> +
> + /* Display WA #1110: skl,kbl,cfl,bxt */
> + if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
> + chicken |= DDI_MASK_INTERRUPTS_PSR;
> + I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
> + }
> }
>
> /**
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