1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
Signed-off-by: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_vdsc.c | 51 +++++++++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7d0574cf6e94..bd2c0832a4dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9676,11 +9676,14 @@ enum skl_power_gate {
#define DSS_CONTROL1 _MMIO(0x67400)
#define JOINER_ENABLE (1 << 30)
+#define JOINER_DISABLE (0 << 30)
#define SPLITTER_ENABLE (1 << 31)
#define DSS_CONTROL2 _MMIO(0x67404)
#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
+#define LEFT_BRANCH_VDSC_DISABLE (0 << 31)
#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
+#define RIGHT_BRANCH_VDSC_DISABLE (0 << 15)
#define PIPE_DSS_CTL1_PB _MMIO(0x78200)
#define PIPE_DSS_CTL2_PB _MMIO(0x78204)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 16f84044f47b..86b2d17df3a8 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1190,3 +1190,54 @@ void intel_dsc_enable(struct intel_encoder *encoder,
I915_WRITE(dsc_regs.dss_ctrl2_reg, dss_ctrl2_value);
}
}
+
+void intel_dsc_disable(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_dsc_regs dsc_regs;
+ struct drm_crtc *crtc = pipe_config->base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ int type = encoder->type;
+ unsigned int dss_ctrl1_value = 0;
+ unsigned int dss_ctrl2_value = 0;
+
+ if ((INTEL_GEN(dev_priv) < 9) ||
+ !intel_dp->compr_params.compression_support)
+ return;
+
+ if (type == INTEL_OUTPUT_EDP) {
+ dsc_regs.dss_ctrl1_reg = DSS_CONTROL1;
+ dsc_regs.dss_ctrl2_reg = DSS_CONTROL2;
+ } else if (type == INTEL_OUTPUT_DP) {
+ switch (pipe) {
+ case PIPE_A:
+ dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PB;
+ dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PB;
+ break;
+ case PIPE_B:
+ dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PC;
+ dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PC;
+ break;
+ default:
+ return;
+ }
+ } else {
+ DRM_ERROR("Func:%s Unsupported port:%d\n", __func__, type);
+ }
+
+ dss_ctrl1_value = I915_READ(dsc_regs.dss_ctrl1_reg);
+ dss_ctrl2_value = I915_READ(dsc_regs.dss_ctrl2_reg);
+
+ if ((dss_ctrl2_value & LEFT_BRANCH_VDSC_ENABLE) ||
+ (dss_ctrl2_value & RIGHT_BRANCH_VDSC_ENABLE))
+ dss_ctrl2_value &= LEFT_BRANCH_VDSC_DISABLE &
+ RIGHT_BRANCH_VDSC_DISABLE;
+ I915_WRITE(dsc_regs.dss_ctrl2_reg, dss_ctrl2_value);
+
+ if (dss_ctrl1_value & JOINER_ENABLE)
+ dss_ctrl1_value &= JOINER_DISABLE;
+ I915_WRITE(dsc_regs.dss_ctrl1_reg, dss_ctrl1_value);
+}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
