Below changes are being taken care in this patch:
1. If there is no DSC support from DPCD offset 0x60, just return
2. If DSC support is there, disable decompression in DPCD offset
0x160 during DP encoder disable sequence.
3. If DSC support is there, enable decompression in DPCD offset
0x160 during DP encoder enable sequence before sending PPS.
Signed-off-by: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
drivers/gpu/drm/i915/intel_dp.c | 14 ++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
include/drm/drm_dp_helper.h | 2 ++
4 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index db92a2691206..693061444d4b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2177,6 +2177,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_ddi_init_dp_buf_reg(encoder);
if (!is_mst)
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+ /* Enable Decompression in DP Sink at DPCD offset 0x00160 offset */
+ intel_dp_sink_set_decompression_state(intel_dp, DECOMPRESSION_ENABLE);
intel_dp_start_link_train(intel_dp);
if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
intel_dp_stop_link_train(intel_dp);
@@ -2480,6 +2482,8 @@ static void intel_disable_ddi_dp(struct intel_encoder *encoder,
intel_edp_drrs_disable(intel_dp, old_crtc_state);
intel_psr_disable(intel_dp, old_crtc_state);
intel_edp_backlight_off(old_conn_state);
+ /* Disable Decompression in DP Sink at DPCD offset 0x00160 offset */
+ intel_dp_sink_set_decompression_state(intel_dp, DECOMPRESSION_DISABLE);
}
static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f494a851ff89..c3b48b214e8f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2538,6 +2538,20 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
}
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ int decomp_state)
+{
+ int ret;
+
+ if (!intel_dp->compr_params.compression_support)
+ return;
+
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, decomp_state);
+ if (ret < 0)
+ DRM_ERROR("DCPD write fail offset:0x%x for decompr state:%d\n",
+ DP_DSC_ENABLE, decomp_state);
+}
+
/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6e1b907990bf..8d8d4486773a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1595,6 +1595,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
void intel_dp_start_link_train(struct intel_dp *intel_dp);
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+ int decomp_state);
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 05f811c50d28..f3f44847c86e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -445,6 +445,8 @@
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
+#define DECOMPRESSION_ENABLE (1 << 0)
+#define DECOMPRESSION_DISABLE 0
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE (1 << 0)
--
1.9.1
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