Quoting Ville Syrjala (2018-02-21 16:02:33) > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > As only a subset of primary planes are FBC capable there's no need > to waste fences on all of them. So let's skip the fence if the plane > isn't even fbc capable. > > In the future we might extend this to skip the fence even for FBC > capable planes if the crtc and/or plane state isn't suitable > for FBC. > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 8aeb6b686bac..b4048b425ffd 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2076,7 +2076,7 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) > if (i915_gem_object_get_tiling(obj) == I915_TILING_NONE) > return false; > > - return INTEL_GEN(dev_priv) < 4 || plane->id == PLANE_PRIMARY; > + return INTEL_GEN(dev_priv) < 4 || plane->has_fbc; Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
