== Series Details == Series: Adding NV12 support (rev12) URL : https://patchwork.freedesktop.org/series/28103/ State : warning == Summary == $ dim checkpatch origin/drm-tip bcaef9063e6b drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values 2f18b9726ab8 drm/i915/skl+: refactor WM calculation for NV12 -:180: CHECK: Prefer kernel type 'u16' over 'uint16_t' #180: FILE: drivers/gpu/drm/i915/intel_pm.c:4161: + uint16_t *minimum, uint16_t *uv_minimum) -:198: CHECK: Prefer kernel type 'u16' over 'uint16_t' #198: FILE: drivers/gpu/drm/i915/intel_pm.c:4194: + uint16_t uv_minimum[I915_MAX_PLANES] = {}; -:247: CHECK: Prefer kernel type 'u16' over 'uint16_t' #247: FILE: drivers/gpu/drm/i915/intel_pm.c:4258: + uint16_t plane_blocks, uv_plane_blocks; total: 0 errors, 0 warnings, 3 checks, 293 lines checked 8cc4ae0ab64a drm/i915/skl+: add NV12 in skl_format_to_fourcc 3c482886a3e0 drm/i915/skl+: support verification of DDB HW state for NV12 d81bfc5007a6 drm/i915/skl+: NV12 related changes for WM 7f7db5c9f0a5 drm/i915/skl+: pass skl_wm_level struct to wm compute func f9d74e780509 drm/i915/skl+: make sure higher latency level has higher wm value 1799584a0027 drm/i915/skl+: nv12 workaround disable WM level 1-7 739a92a9f739 drm/i915/skl: split skl_compute_ddb function -:113: CHECK: Prefer kernel type 'u32' over 'uint32_t' #113: FILE: drivers/gpu/drm/i915/intel_pm.c:5141: + uint32_t realloc_pipes = pipes_modified(state); -:132: CHECK: spaces preferred around that '*' (ctx:ExV) #132: FILE: drivers/gpu/drm/i915/intel_pm.c:5160: + *changed = true; ^ total: 0 errors, 0 warnings, 2 checks, 194 lines checked debb41aa8125 drm/i915: Set scaler mode for NV12 -:61: CHECK: Prefer using the BIT macro #61: FILE: drivers/gpu/drm/i915/i915_reg.h:6736: +#define PS_SCALER_MODE_PLANAR (1 << 29) total: 0 errors, 0 warnings, 1 checks, 27 lines checked 80d7e4fdc8e1 drm/i915: Update format_is_yuv() to include NV12 18c91d98376c drm/i915: Upscale scaler max scale for NV12 -:152: CHECK: Prefer kernel type 'u32' over 'uint32_t' #152: FILE: drivers/gpu/drm/i915/intel_display.c:12860: + uint32_t pixel_format = 0; total: 0 errors, 0 warnings, 1 checks, 119 lines checked b804cd678b39 drm/i915: Add NV12 as supported format for primary plane c2060bb9afa8 drm/i915: Add NV12 as supported format for sprite plane a9e9ba5791b7 drm/i915: Add NV12 support to intel_framebuffer_init -:64: WARNING: line over 80 characters #64: FILE: drivers/gpu/drm/i915/intel_display.c:14096: + drm_get_format_name(mode_cmd->pixel_format, -:65: CHECK: Alignment should match open parenthesis #65: FILE: drivers/gpu/drm/i915/intel_display.c:14097: + drm_get_format_name(mode_cmd->pixel_format, + &format_name)); total: 0 errors, 1 warnings, 1 checks, 14 lines checked 26664b13b281 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg -:27: CHECK: Prefer using the BIT macro #27: FILE: drivers/gpu/drm/i915/i915_reg.h:6458: +#define PLANE_COLOR_YUV601_TO_RGB709 (1 << 17) total: 0 errors, 0 warnings, 1 checks, 20 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
