On Fri, 2018-02-16 at 08:55 +0000, Chris Wilson wrote:
> Quoting Dhinakaran Pandiyan (2018-02-16 04:33:21)
> > Preparing a framebuffer should not require a flush. _post_plane_update()
> > takes care of flushing when a flip is scheduled, this should be
> > sufficient for PSR and FBC.
>
> Makes sense.
>
I also think this might speed up the flips a bit by avoiding flushes.
> > Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
>
> Also
> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> to validate the flow through atomic.
> -Chris
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 6 ++----
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 24ca43424c44..c611855bf05a 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -12717,12 +12717,10 @@ intel_prepare_plane_fb(struct drm_plane *plane,
> > struct i915_vma *vma;
> >
> > vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
> > - if (!IS_ERR(vma)) {
> > + if (!IS_ERR(vma))
> > to_intel_plane_state(new_state)->vma = vma;
> > - intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
> > - } else {
> > + else
> > ret = PTR_ERR(vma);
> > - }
> > }
> >
> > i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
> > --
> > 2.14.1
> >
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