On Thu, 15 Feb 2018, Mahesh Kumar <mahesh1.kumar@xxxxxxxxx> wrote:
> Register Address for CNL_PORT_DW5_LN0_D is 0x162E54, but current code is
> defining it as 0x162ED4. Similarly for CNL_PORT_DW7_LN0_D register address
> is defined 0x162EDC instead of 0x162E5C, fix it.
Which commit introduced the bug? Please add Fixes: annotation for it. We
want this backported.
BR,
Jani.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6afa5e5e7c1..1412abcb27d4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2034,7 +2034,7 @@ enum i915_power_well_id {
> #define _CNL_PORT_TX_DW5_LN0_AE 0x162454
> #define _CNL_PORT_TX_DW5_LN0_B 0x162654
> #define _CNL_PORT_TX_DW5_LN0_C 0x162C54
> -#define _CNL_PORT_TX_DW5_LN0_D 0x162ED4
> +#define _CNL_PORT_TX_DW5_LN0_D 0x162E54
> #define _CNL_PORT_TX_DW5_LN0_F 0x162854
> #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
> _CNL_PORT_TX_DW5_GRP_AE, \
> @@ -2065,7 +2065,7 @@ enum i915_power_well_id {
> #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
> #define _CNL_PORT_TX_DW7_LN0_B 0x16265C
> #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
> -#define _CNL_PORT_TX_DW7_LN0_D 0x162EDC
> +#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C
> #define _CNL_PORT_TX_DW7_LN0_F 0x16285C
> #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
> _CNL_PORT_TX_DW7_GRP_AE, \
--
Jani Nikula, Intel Open Source Technology Center
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