== Series Details == Series: ICL GEM enabling (v2) (rev2) URL : https://patchwork.freedesktop.org/series/38174/ State : warning == Summary == $ dim checkpatch origin/drm-tip e3d750591349 drm/i915/icl: Add the ICL PCI IDs -:47: ERROR: Macros with complex values should be enclosed in parentheses #47: FILE: include/drm/i915_pciids.h:434: +#define INTEL_ICL_11_IDS(info) \ + INTEL_VGA_DEVICE(0x8A50, info), \ + INTEL_VGA_DEVICE(0x8A51, info), \ + INTEL_VGA_DEVICE(0x8A5C, info), \ + INTEL_VGA_DEVICE(0x8A5D, info), \ + INTEL_VGA_DEVICE(0x8A52, info), \ + INTEL_VGA_DEVICE(0x8A5A, info), \ + INTEL_VGA_DEVICE(0x8A5B, info), \ + INTEL_VGA_DEVICE(0x8A71, info), \ + INTEL_VGA_DEVICE(0x8A70, info) -:47: CHECK: Macro argument reuse 'info' - possible side-effects? #47: FILE: include/drm/i915_pciids.h:434: +#define INTEL_ICL_11_IDS(info) \ + INTEL_VGA_DEVICE(0x8A50, info), \ + INTEL_VGA_DEVICE(0x8A51, info), \ + INTEL_VGA_DEVICE(0x8A5C, info), \ + INTEL_VGA_DEVICE(0x8A5D, info), \ + INTEL_VGA_DEVICE(0x8A52, info), \ + INTEL_VGA_DEVICE(0x8A5A, info), \ + INTEL_VGA_DEVICE(0x8A5B, info), \ + INTEL_VGA_DEVICE(0x8A71, info), \ + INTEL_VGA_DEVICE(0x8A70, info) total: 1 errors, 0 warnings, 1 checks, 23 lines checked d75493c4335d drm/i915/icl: add icelake_init_clock_gating() -:22: CHECK: Blank lines aren't necessary after an open brace '{' #22: FILE: drivers/gpu/drm/i915/intel_pm.c:8498: +{ + -:23: CHECK: Blank lines aren't necessary before a close brace '}' #23: FILE: drivers/gpu/drm/i915/intel_pm.c:8499: + +} total: 0 errors, 0 warnings, 2 checks, 21 lines checked 048837d73700 drm/i915/icl: Show interrupt registers in debugfs 145a0e361111 drm/i915/icl: Prepare for more rings 21129ec5a1e2 drm/i915/icl: Interrupt handling -:88: WARNING: line over 80 characters #88: FILE: drivers/gpu/drm/i915/i915_irq.c:2780: + I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit); -:90: WARNING: line over 80 characters #90: FILE: drivers/gpu/drm/i915/i915_irq.c:2782: + /* NB: Specs do not specify how long to spin wait. -:91: WARNING: Block comments use a trailing */ on a separate line #91: FILE: drivers/gpu/drm/i915/i915_irq.c:2783: + * Taking 100us as an educated guess */ -:94: WARNING: line over 80 characters #94: FILE: drivers/gpu/drm/i915/i915_irq.c:2786: + ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank)); -:96: WARNING: line over 80 characters #96: FILE: drivers/gpu/drm/i915/i915_irq.c:2788: + !time_after((unsigned long)local_clock() >> 10, wait_end)); -:99: WARNING: line over 80 characters #99: FILE: drivers/gpu/drm/i915/i915_irq.c:2791: + DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n", -:104: WARNING: line over 80 characters #104: FILE: drivers/gpu/drm/i915/i915_irq.c:2796: + DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n", -:106: WARNING: line over 80 characters #106: FILE: drivers/gpu/drm/i915/i915_irq.c:2798: + I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident); total: 0 errors, 8 warnings, 0 checks, 265 lines checked 35e3bee64402 drm/i915/icl: Ringbuffer interrupt handling f3825b9b7935 drm/i915/icl: Correctly initialize the Gen11 engines e535dcb288c4 drm/i915/icl: new context descriptor support -:37: CHECK: spaces preferred around that '<<' (ctx:VxV) #37: FILE: drivers/gpu/drm/i915/i915_drv.h:2099: +#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ ^ -:37: CHECK: Prefer using the BIT macro #37: FILE: drivers/gpu/drm/i915/i915_drv.h:2099: +#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ -:121: CHECK: spaces preferred around that '<<' (ctx:VxV) #121: FILE: drivers/gpu/drm/i915/intel_lrc.c:211: + BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (1<<GEN11_SW_CTX_ID_WIDTH)); ^ total: 0 errors, 0 warnings, 3 checks, 92 lines checked ea7cec009f3b drm/i915/icl: Enhanced execution list support -:81: WARNING: line over 80 characters #81: FILE: drivers/gpu/drm/i915/intel_lrc.c:402: +static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port) -:87: WARNING: line over 80 characters #87: FILE: drivers/gpu/drm/i915/intel_lrc.c:406: + writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1); -:199: WARNING: line over 80 characters #199: FILE: drivers/gpu/drm/i915/intel_lrc.h:45: +#define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510) -:200: WARNING: line over 80 characters #200: FILE: drivers/gpu/drm/i915/intel_lrc.h:46: +#define RING_EXECLIST_CONTROL(engine) _MMIO((engine)->mmio_base + 0x550) -:201: CHECK: Prefer using the BIT macro #201: FILE: drivers/gpu/drm/i915/intel_lrc.h:47: +#define EL_CTRL_LOAD (1 << 0) total: 0 errors, 4 warnings, 1 checks, 161 lines checked c3f217cfec40 drm/i915/icl: Add Indirect Context Offset for Gen11 96cf65e43227 drm/i915/icl: Gen11 forcewake support -:81: CHECK: Macro argument reuse 'reg' - possible side-effects? #81: FILE: drivers/gpu/drm/i915/intel_uncore.c:783: +#define GEN11_NEEDS_FORCE_WAKE(reg) \ + ((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000)) -:106: CHECK: Macro argument reuse 'offset' - possible side-effects? #106: FILE: drivers/gpu/drm/i915/intel_uncore.c:880: +#define __gen11_fwtable_reg_read_fw_domains(offset) \ +({ \ + enum forcewake_domains __fwd = 0; \ + if (GEN11_NEEDS_FORCE_WAKE((offset))) \ + __fwd = find_fw_domain(dev_priv, offset); \ + __fwd; \ +}) -:166: CHECK: Macro argument reuse 'offset' - possible side-effects? #166: FILE: drivers/gpu/drm/i915/intel_uncore.c:974: +#define __gen11_fwtable_reg_write_fw_domains(offset) \ +({ \ + enum forcewake_domains __fwd = 0; \ + if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \ + __fwd = find_fw_domain(dev_priv, offset); \ + __fwd; \ +}) -:263: WARNING: line over 80 characters #263: FILE: drivers/gpu/drm/i915/intel_uncore.c:1338: + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); -:264: WARNING: line over 80 characters #264: FILE: drivers/gpu/drm/i915/intel_uncore.c:1339: + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); -:265: WARNING: line over 80 characters #265: FILE: drivers/gpu/drm/i915/intel_uncore.c:1340: + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); -:266: WARNING: line over 80 characters #266: FILE: drivers/gpu/drm/i915/intel_uncore.c:1341: + BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); -:267: WARNING: line over 80 characters #267: FILE: drivers/gpu/drm/i915/intel_uncore.c:1342: + BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); -:268: WARNING: line over 80 characters #268: FILE: drivers/gpu/drm/i915/intel_uncore.c:1343: + BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); total: 0 errors, 6 warnings, 3 checks, 360 lines checked 505af6b68524 drm/i915/icl: Check for fused-off VDBOX and VEBOX instances -:8: WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line) #8: each VDBOX and VEBOX has its own power well, which only exist if the related -:34: ERROR: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 33def1ff7b09 ("drm/i915: Simplify intel_engines_init")' #34: commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init") total: 1 errors, 1 warnings, 0 checks, 83 lines checked 507d86de0ad8 drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11 a92d8fb69ff7 drm/i915/icl: Update subslice define for ICL 11 -:44: CHECK: Prefer kernel type 'u32' over 'uint32_t' #44: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:781: + uint32_t mcr_slice_subslice_mask; -:45: CHECK: Prefer kernel type 'u32' over 'uint32_t' #45: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:782: + uint32_t mcr_slice_subslice_select; total: 0 errors, 0 warnings, 2 checks, 60 lines checked 5d1119aba0bb drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection d1a20b90b203 drm/i915/icl: Add reset control register changes -:35: CHECK: Prefer using the BIT macro #35: FILE: drivers/gpu/drm/i915/i915_reg.h:310: +#define GEN11_GRDOM_BLT (1 << 2) -:36: CHECK: Prefer using the BIT macro #36: FILE: drivers/gpu/drm/i915/i915_reg.h:311: +#define GEN11_GRDOM_GUC (1 << 3) -:37: CHECK: Prefer using the BIT macro #37: FILE: drivers/gpu/drm/i915/i915_reg.h:312: +#define GEN11_GRDOM_MEDIA (1 << 5) -:38: CHECK: Prefer using the BIT macro #38: FILE: drivers/gpu/drm/i915/i915_reg.h:313: +#define GEN11_GRDOM_MEDIA2 (1 << 6) -:39: CHECK: Prefer using the BIT macro #39: FILE: drivers/gpu/drm/i915/i915_reg.h:314: +#define GEN11_GRDOM_MEDIA3 (1 << 7) -:40: CHECK: Prefer using the BIT macro #40: FILE: drivers/gpu/drm/i915/i915_reg.h:315: +#define GEN11_GRDOM_MEDIA4 (1 << 8) -:41: CHECK: Prefer using the BIT macro #41: FILE: drivers/gpu/drm/i915/i915_reg.h:316: +#define GEN11_GRDOM_VECS (1 << 13) -:42: CHECK: Prefer using the BIT macro #42: FILE: drivers/gpu/drm/i915/i915_reg.h:317: +#define GEN11_GRDOM_VECS2 (1 << 14) -:67: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' #67: FILE: drivers/gpu/drm/i915/intel_uncore.c:1870: + unsigned engine_mask) total: 0 errors, 1 warnings, 8 checks, 93 lines checked d69bf1391650 drm/i915/icl: Add configuring MOCS in new Icelake engines -:6: WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: In Icelake, there are more engines on which Memory Object Control States need total: 0 errors, 1 warnings, 0 checks, 25 lines checked 69f0d8dbe77e drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers -:100: WARNING: line over 80 characters #100: FILE: drivers/gpu/drm/i915/i915_irq.c:2811: + gen11_service_shared_iir(dev_priv, bank, bit); total: 0 errors, 1 warnings, 0 checks, 78 lines checked feef482fb7f3 drm/i915/icl: Handle RPS interrupts correctly for Gen11 -:92: WARNING: line over 80 characters #92: FILE: drivers/gpu/drm/i915/i915_irq.c:488: + WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); total: 0 errors, 1 warnings, 0 checks, 148 lines checked 2a584d53b971 drm/i915/icl: Enable RC6 and RPS in Gen11 -:58: WARNING: line over 80 characters #58: FILE: drivers/gpu/drm/i915/i915_debugfs.c:1831: + INTEL_GEN(dev_priv) >= 10 ? total: 0 errors, 1 warnings, 0 checks, 79 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
