On Fri, Feb 09, 2018 at 09:16:54PM +0000, Chris Wilson wrote:
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> drivers/gpu/drm/i915/intel_fbc.c | 3 ++-
> 4 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a662d5f28080..8bf782b08fe0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2807,7 +2807,7 @@ runtime_info(const struct drm_i915_private *dev_priv)
> #define I915_HAS_HOTPLUG(dev_priv) (DEVICE_INFO(dev_priv)->has_hotplug)
>
> #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
> -#define HAS_FBC(dev_priv) (DEVICE_INFO(dev_priv)->has_fbc)
> +#define HAS_FBC(dev_priv) (DEVICE_INFO(dev_priv)->has_fbc & RUNTIME_INFO(dev_priv)->has_fbc)
> #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && DEVICE_INFO(dev_priv)->gen >= 7)
>
> #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 1a5b2c1c9df9..580ca5b0a1e3 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -587,6 +587,7 @@ void intel_device_runtime_info_print(const struct intel_device_runtime_info *inf
> sseu_dump(&info->sseu, p);
>
> drm_printf(p, "Num display pipes: %d\n", info->num_pipes);
> + drm_printf(p, "Has FBC: %s\n", yesno(info->has_fbc));
> }
>
> void intel_driver_caps_print(const struct intel_driver_caps *caps,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 09e0200f7afa..3f21b3ea25b1 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -167,6 +167,8 @@ struct intel_device_runtime_info { /* device info probed at runtime */
> u8 num_sprites[I915_MAX_PIPES];
> u8 num_scalers[I915_MAX_PIPES];
>
> + bool has_fbc:1;
> +
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
>
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index d7d1ac79c38a..73aa904f7f56 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -1361,8 +1361,9 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
> fbc->active = false;
> fbc->work.scheduled = false;
>
> + dev_priv->device_runtime.has_fbc = DEVICE_INFO(dev_priv)->has_fbc;
> if (need_fbc_vtd_wa(dev_priv))
> - mkwrite_device_info(dev_priv)->has_fbc = false;
> + dev_priv->device_runtime.has_fbc = false;
IIRC I sent a patch series adding a plane->has_fbc, so if we were to
have that we might not need this one. Not sure. But I suppose there
isn't much harm in having this in the runtime info though, and we
can always revisit it later.
>
> i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
> DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
> --
> 2.16.1
>
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--
Ville Syrjälä
Intel OTC
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