add/remove: 1/2 grow/shrink: 11/60 up/down: 3337/-3770 (-433)
Function old new delta
intel_device_runtime_info_init - 2632 +2632
intel_device_runtime_info_print 25 335 +310
capture 6174 6387 +213
i915_driver_load 4990 5119 +129
init_ring_common 1717 1733 +16
intel_psr_compute_config 483 492 +9
intel_psr_single_frame_update 162 170 +8
intel_psr_init 591 599 +8
intel_psr_enable 328 332 +4
execlists_init_reg_state.isra 1285 1289 +4
intel_runtime_suspend 612 615 +3
intel_setup_overlay 902 903 +1
i915_gem_do_execbuffer 5608 5607 -1
config_status 100 98 -2
intel_overlay_put_image_ioctl 4986 4983 -3
intel_device_info_dump 82 79 -3
intel_rc6_residency_ns 356 352 -4
i915_getparam 707 702 -5
intel_enable_gt_powersave 6309 6303 -6
intel_engine_init_common 1121 1114 -7
intel_psr_disable 214 206 -8
i915_capabilities 230 212 -18
intel_valleyview_info 132 112 -20
intel_skylake_gt4_info 132 112 -20
intel_skylake_gt3_info 132 112 -20
intel_skylake_gt2_info 132 112 -20
intel_skylake_gt1_info 132 112 -20
intel_sandybridge_m_gt2_info 132 112 -20
intel_sandybridge_m_gt1_info 132 112 -20
intel_sandybridge_d_gt2_info 132 112 -20
intel_sandybridge_d_gt1_info 132 112 -20
intel_pineview_info 132 112 -20
intel_kabylake_gt3_info 132 112 -20
intel_kabylake_gt2_info 132 112 -20
intel_kabylake_gt1_info 132 112 -20
intel_ivybridge_q_info 132 112 -20
intel_ivybridge_m_gt2_info 132 112 -20
intel_ivybridge_m_gt1_info 132 112 -20
intel_ivybridge_d_gt2_info 132 112 -20
intel_ivybridge_d_gt1_info 132 112 -20
intel_ironlake_m_info 132 112 -20
intel_ironlake_d_info 132 112 -20
intel_i965gm_info 132 112 -20
intel_i965g_info 132 112 -20
intel_i945gm_info 132 112 -20
intel_i945g_info 132 112 -20
intel_i915gm_info 132 112 -20
intel_i915g_info 132 112 -20
intel_i865g_info 132 112 -20
intel_i85x_info 132 112 -20
intel_i845g_info 132 112 -20
intel_i830_info 132 112 -20
intel_haswell_gt3_info 132 112 -20
intel_haswell_gt2_info 132 112 -20
intel_haswell_gt1_info 132 112 -20
intel_gm45_info 132 112 -20
intel_geminilake_info 132 112 -20
intel_g45_info 132 112 -20
intel_g33_info 132 112 -20
intel_coffeelake_gt3_info 132 112 -20
intel_coffeelake_gt2_info 132 112 -20
intel_coffeelake_gt1_info 132 112 -20
intel_cherryview_info 132 112 -20
intel_cannonlake_info 132 112 -20
intel_broxton_info 132 112 -20
intel_broadwell_rsvd_info 132 112 -20
intel_broadwell_gt3_info 132 112 -20
intel_broadwell_gt2_info 132 112 -20
intel_broadwell_gt1_info 132 112 -20
i915_print_sseu_info 433 404 -29
intel_init_gt_powersave 3091 3061 -30
intel_device_info_dump_flags 1226 1192 -34
intel_device_info_dump_runtime 299 - -299
intel_device_info_runtime_init 2381 - -2381
Total: Before=1331260, After=1330827, chg -0.03%
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++------------
drivers/gpu/drm/i915/i915_drv.c | 31 +++++++++++++-------------
drivers/gpu/drm/i915/i915_drv.h | 5 ++++-
drivers/gpu/drm/i915/i915_pci.c | 1 -
drivers/gpu/drm/i915/i915_perf.c | 4 ++--
drivers/gpu/drm/i915/intel_audio.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 38 ++++++++++++++------------------
drivers/gpu/drm/i915/intel_device_info.h | 23 ++++++++++---------
drivers/gpu/drm/i915/intel_display.c | 13 +++++------
drivers/gpu/drm/i915/intel_display.h | 10 ++++-----
drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/intel_fbdev.c | 2 +-
drivers/gpu/drm/i915/intel_lpe_audio.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 14 ++++++------
drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++--
drivers/gpu/drm/i915/intel_pm.c | 7 +++---
drivers/gpu/drm/i915/intel_ringbuffer.h | 6 ++---
17 files changed, 89 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d973e59464e2..a7c96b609b48 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -48,7 +48,6 @@ static int i915_capabilities(struct seq_file *m, void *data)
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
intel_device_info_dump_flags(info, &p);
- intel_device_info_dump_runtime(info, &p);
intel_device_runtime_info_print(&dev_priv->device_runtime, &p);
intel_driver_caps_print(&dev_priv->caps, &p);
@@ -3147,7 +3146,7 @@ static int i915_engine_info(struct seq_file *m, void *unused)
seq_printf(m, "Global active requests: %d\n",
dev_priv->gt.active_requests);
seq_printf(m, "CS timestamp frequency: %u kHz\n",
- DEVICE_INFO(dev_priv)->cs_timestamp_frequency_khz);
+ RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
p = drm_seq_file_printer(m);
for_each_engine(engine, dev_priv, id)
@@ -4295,7 +4294,6 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
- const struct intel_device_static_info *info = DEVICE_INFO(dev_priv);
int s_max = 6, ss_max = 4;
int s, ss;
u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
@@ -4328,7 +4326,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
continue;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask = info->sseu.subslice_mask;
+ sseu->subslice_mask = INTEL_SSEU(dev_priv)->subslice_mask;
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4383,8 +4381,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask =
- DEVICE_INFO(dev_priv)->sseu.subslice_mask;
+ sseu->subslice_mask = INTEL_SSEU(dev_priv)->subslice_mask;
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -4416,16 +4413,14 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
if (sseu->slice_mask) {
- sseu->subslice_mask = DEVICE_INFO(dev_priv)->sseu.subslice_mask;
- sseu->eu_per_subslice =
- DEVICE_INFO(dev_priv)->sseu.eu_per_subslice;
+ sseu->subslice_mask = INTEL_SSEU(dev_priv)->subslice_mask;
+ sseu->eu_per_subslice = INTEL_SSEU(dev_priv)->eu_per_subslice;
sseu->eu_total = sseu->eu_per_subslice *
sseu_subslice_total(sseu);
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
- u8 subslice_7eu =
- DEVICE_INFO(dev_priv)->sseu.subslice_7eu[s];
+ u8 subslice_7eu = INTEL_SSEU(dev_priv)->subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -4435,7 +4430,6 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
const struct sseu_dev_info *sseu)
{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
const char *type = is_available_info ? "Available" : "Enabled";
seq_printf(m, " %s Slice Mask: %04x\n", type,
@@ -4456,8 +4450,8 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
if (!is_available_info)
return;
- seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
- if (HAS_POOLED_EU(dev_priv))
+ seq_printf(m, " Has Pooled EU: %s\n", yesno(sseu->has_pooled_eu));
+ if (sseu->has_pooled_eu)
seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
seq_printf(m, " Has Slice Power Gating: %s\n",
@@ -4477,7 +4471,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
- i915_print_sseu_info(m, true, &DEVICE_INFO(dev_priv)->sseu);
+ i915_print_sseu_info(m, true, INTEL_SSEU(dev_priv));
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index dfb6227f5cc9..a0ded5360d18 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -165,7 +165,7 @@ static void intel_detect_pch(struct drm_i915_private *dev_priv)
/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
* (which really amounts to a PCH but no South Display).
*/
- if (DEVICE_INFO(dev_priv)->num_pipes == 0) {
+ if (NUM_PIPES(dev_priv) == 0) {
dev_priv->pch_type = PCH_NOP;
return;
}
@@ -344,12 +344,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = sseu_subslice_total(&DEVICE_INFO(dev_priv)->sseu);
+ value = sseu_subslice_total(INTEL_SSEU(dev_priv));
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = DEVICE_INFO(dev_priv)->sseu.eu_total;
+ value = INTEL_SSEU(dev_priv)->eu_total;
if (!value)
return -ENODEV;
break;
@@ -363,10 +363,10 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = HAS_RESOURCE_STREAMER(dev_priv);
break;
case I915_PARAM_HAS_POOLED_EU:
- value = HAS_POOLED_EU(dev_priv);
+ value = INTEL_SSEU(dev_priv)->has_pooled_eu;
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = DEVICE_INFO(dev_priv)->sseu.min_eu_in_pool;
+ value = INTEL_SSEU(dev_priv)->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
intel_runtime_pm_get(dev_priv);
@@ -416,17 +416,17 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = intel_engines_has_context_isolation(dev_priv);
break;
case I915_PARAM_SLICE_MASK:
- value = DEVICE_INFO(dev_priv)->sseu.slice_mask;
+ value = INTEL_SSEU(dev_priv)->slice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_SUBSLICE_MASK:
- value = DEVICE_INFO(dev_priv)->sseu.subslice_mask;
+ value = INTEL_SSEU(dev_priv)->subslice_mask;
if (!value)
return -ENODEV;
break;
case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
- value = 1000 * DEVICE_INFO(dev_priv)->cs_timestamp_frequency_khz;
+ value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
@@ -692,7 +692,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_setup_overlay(dev_priv);
- if (DEVICE_INFO(dev_priv)->num_pipes == 0)
+ if (NUM_PIPES(dev_priv) == 0)
return 0;
ret = intel_fbdev_init(dev);
@@ -1088,7 +1088,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
if (i915_inject_load_failure())
return -ENODEV;
- intel_device_info_runtime_init(mkwrite_device_info(dev_priv));
+ intel_device_runtime_info_init(dev_priv);
intel_sanitize_options(dev_priv);
@@ -1240,7 +1240,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
} else
DRM_ERROR("Failed to register driver for userspace access!\n");
- if (DEVICE_INFO(dev_priv)->num_pipes) {
+ if (NUM_PIPES(dev_priv)) {
/* Must be done after probing outputs */
intel_opregion_register(dev_priv);
acpi_video_register();
@@ -1264,7 +1264,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
* We need to coordinate the hotplugs with the asynchronous fbdev
* configuration, for which we use the fbdev->async_cookie.
*/
- if (DEVICE_INFO(dev_priv)->num_pipes)
+ if (NUM_PIPES(dev_priv))
drm_kms_helper_poll_init(dev);
}
@@ -1304,7 +1304,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
struct drm_printer p = drm_debug_printer("i915 device info:");
intel_device_info_dump(&dev_priv->device_static, &p);
- intel_device_info_dump_runtime(&dev_priv->device_static, &p);
+ intel_device_runtime_info_print(&dev_priv->device_runtime, &p);
}
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
@@ -1381,9 +1381,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
* of the i915_driver_init_/i915_driver_register functions according
* to the role/effect of the given init step.
*/
- if (DEVICE_INFO(dev_priv)->num_pipes) {
- ret = drm_vblank_init(&dev_priv->drm,
- DEVICE_INFO(dev_priv)->num_pipes);
+ if (NUM_PIPES(dev_priv)) {
+ ret = drm_vblank_init(&dev_priv->drm, NUM_PIPES(dev_priv));
if (ret)
goto out_cleanup_hw;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 270adb157186..4383a76c9522 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2849,7 +2849,10 @@ runtime_info(const struct drm_i915_private *dev_priv)
#define HAS_RESOURCE_STREAMER(dev_priv) (DEVICE_INFO(dev_priv)->has_resource_streamer)
-#define HAS_POOLED_EU(dev_priv) (DEVICE_INFO(dev_priv)->has_pooled_eu)
+#define INTEL_SSEU(dev_priv__) (&RUNTIME_INFO(dev_priv__)->sseu)
+#define HAS_POOLED_EU(dev_priv) (INTEL_SSEU(dev_priv)->has_pooled_eu)
+
+#define NUM_PIPES(dev_priv) (RUNTIME_INFO(dev_priv)->num_pipes)
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 53639b72315d..669b5c049349 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -506,7 +506,6 @@ static const struct intel_device_static_info intel_skylake_gt4_info = {
.has_fbc = 1, \
.has_psr = 1, \
.has_runtime_pm = 1, \
- .has_pooled_eu = 0, \
.has_csr = 1, \
.has_resource_streamer = 1, \
.has_rc6 = 1, \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ecf883e99902..f9d5db3c6e06 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2691,7 +2691,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
{
return div64_u64(1000000000ULL * (2ULL << exponent),
- 1000ULL * DEVICE_INFO(dev_priv)->cs_timestamp_frequency_khz);
+ 1000ULL * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
}
/**
@@ -3510,7 +3510,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
oa_sample_rate_hard_limit = 1000 *
- (DEVICE_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
+ (RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
mutex_init(&dev_priv->perf.metrics_lock);
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 0c8276fb3591..45ad33102986 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -950,7 +950,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv)
{
int ret;
- if (DEVICE_INFO(dev_priv)->num_pipes == 0)
+ if (NUM_PIPES(dev_priv) == 0)
return;
ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 32a5d4b99510..79d5d5eb4471 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -96,15 +96,6 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
}
-void intel_device_info_dump_runtime(const struct intel_device_static_info *info,
- struct drm_printer *p)
-{
- sseu_dump(&info->sseu, p);
-
- drm_printf(p, "CS timestamp frequency: %u kHz\n",
- info->cs_timestamp_frequency_khz);
-}
-
void intel_device_info_dump(const struct intel_device_static_info *info,
struct drm_printer *p)
{
@@ -122,7 +113,7 @@ void intel_device_info_dump(const struct intel_device_static_info *info,
static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ struct sseu_dev_info *sseu = &dev_priv->device_runtime.sseu;
const u32 fuse2 = I915_READ(GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
@@ -155,7 +146,7 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ struct sseu_dev_info *sseu = &dev_priv->device_runtime.sseu;
u32 fuse, eu_dis;
fuse = I915_READ(CHV_FUSE_GT);
@@ -195,8 +186,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct intel_device_static_info *info = mkwrite_device_info(dev_priv);
- struct sseu_dev_info *sseu = &info->sseu;
+ struct sseu_dev_info *sseu = &dev_priv->device_runtime.sseu;
int s_max = 3, ss_max = 4, eu_max = 8;
int s, ss;
u32 fuse2, eu_disable;
@@ -271,10 +261,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
if (IS_GEN9_LP(dev_priv)) {
#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask & BIT(ss)))
- info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
+ sseu->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
sseu->min_eu_in_pool = 0;
- if (info->has_pooled_eu) {
+ if (sseu->has_pooled_eu) {
if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
sseu->min_eu_in_pool = 3;
else if (IS_SS_DISABLED(1))
@@ -288,7 +278,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+ struct sseu_dev_info *sseu = &dev_priv->device_runtime.sseu;
const int s_max = 3, ss_max = 3, eu_max = 8;
int s, ss;
u32 fuse2, eu_disable[3]; /* s_max */
@@ -459,8 +449,8 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
}
/**
- * intel_device_info_runtime_init - initialize runtime info
- * @info: intel device info struct
+ * intel_device_runtime_info_init - initialize runtime info
+ * @i915: the i915 device
*
* Determine various intel_device_static_info fields at runtime.
*
@@ -474,10 +464,9 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
* - after the PCH has been detected,
* - before the first usage of the fields it can tweak.
*/
-void intel_device_info_runtime_init(struct intel_device_static_info *info)
+void intel_device_runtime_info_init(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv =
- container_of(info, struct drm_i915_private, device_static);
+ struct intel_device_runtime_info *info = &dev_priv->device_runtime;
enum pipe pipe;
if (INTEL_GEN(dev_priv) >= 10) {
@@ -512,6 +501,7 @@ void intel_device_info_runtime_init(struct intel_device_static_info *info)
info->num_sprites[pipe] = 1;
}
+ info->num_pipes = DEVICE_INFO(dev_priv)->num_pipes;
if (i915_modparams.disable_display) {
DRM_INFO("Display disabled (module parameter)\n");
info->num_pipes = 0;
@@ -591,6 +581,12 @@ void intel_device_runtime_info_print(const struct intel_device_runtime_info *inf
struct drm_printer *p)
{
drm_printf(p, "EDRAM: %x\n", info->edram);
+ drm_printf(p, "CS timestamp frequency: %u kHz\n",
+ info->cs_timestamp_frequency_khz);
+
+ sseu_dump(&info->sseu, p);
+
+ drm_printf(p, "Num display pipes: %d\n", info->num_pipes);
}
void intel_driver_caps_print(const struct intel_driver_caps *caps,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 8a570f75d67e..d5f34f124e34 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -98,7 +98,6 @@ enum intel_platform {
func(has_logical_ring_contexts); \
func(has_logical_ring_preemption); \
func(has_overlay); \
- func(has_pooled_eu); \
func(has_psr); \
func(has_rc6); \
func(has_rc6p); \
@@ -123,6 +122,7 @@ struct sseu_dev_info {
u8 has_slice_pg:1;
u8 has_subslice_pg:1;
u8 has_eu_pg:1;
+ u8 has_pooled_eu:1;
};
struct intel_device_static_info {
@@ -139,8 +139,6 @@ struct intel_device_static_info {
u32 display_mmio_offset;
u8 num_pipes;
- u8 num_sprites[I915_MAX_PIPES];
- u8 num_scalers[I915_MAX_PIPES];
unsigned int page_sizes; /* page sizes supported by the HW */
@@ -155,11 +153,6 @@ struct intel_device_static_info {
int palette_offsets[I915_MAX_PIPES];
int cursor_offsets[I915_MAX_PIPES];
- /* Slice/subslice/EU info */
- struct sseu_dev_info sseu;
-
- u32 cs_timestamp_frequency_khz;
-
struct color_luts {
u16 degamma_lut_size;
u16 gamma_lut_size;
@@ -169,6 +162,15 @@ struct intel_device_static_info {
struct intel_device_runtime_info { /* device info probed at runtime */
u32 edram; /* Cannot be determined by PCIID, only from a register. */
u16 device_id;
+
+ u8 num_pipes;
+ u8 num_sprites[I915_MAX_PIPES];
+ u8 num_scalers[I915_MAX_PIPES];
+
+ /* Slice/subslice/EU info */
+ struct sseu_dev_info sseu;
+
+ u32 cs_timestamp_frequency_khz;
};
struct intel_driver_caps {
@@ -182,13 +184,12 @@ static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
const char *intel_platform_name(enum intel_platform platform);
-void intel_device_info_runtime_init(struct intel_device_static_info *info);
+void intel_device_runtime_info_init(struct drm_i915_private *i915);
+
void intel_device_info_dump(const struct intel_device_static_info *info,
struct drm_printer *p);
void intel_device_info_dump_flags(const struct intel_device_static_info *info,
struct drm_printer *p);
-void intel_device_info_dump_runtime(const struct intel_device_static_info *info,
- struct drm_printer *p);
void intel_device_runtime_info_print(const struct intel_device_runtime_info *info,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 931e6c2bd245..5fcee8c9fb7c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13390,7 +13390,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int i;
- crtc->num_scalers = DEVICE_INFO(dev_priv)->num_scalers[crtc->pipe];
+ crtc->num_scalers = RUNTIME_INFO(dev_priv)->num_scalers[crtc->pipe];
if (!crtc->num_scalers)
return;
@@ -14556,7 +14556,7 @@ int intel_modeset_init(struct drm_device *dev)
intel_init_pm(dev_priv);
- if (DEVICE_INFO(dev_priv)->num_pipes == 0)
+ if (NUM_PIPES(dev_priv) == 0)
return 0;
/*
@@ -14602,8 +14602,7 @@ int intel_modeset_init(struct drm_device *dev)
dev->mode_config.fb_base = ggtt->gmadr.start;
DRM_DEBUG_KMS("%d display pipe%s available.\n",
- DEVICE_INFO(dev_priv)->num_pipes,
- DEVICE_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
+ NUM_PIPES(dev_priv), NUM_PIPES(dev_priv) > 1 ? "s" : "");
for_each_pipe(dev_priv, pipe) {
int ret;
@@ -15443,7 +15442,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
};
int i;
- if (DEVICE_INFO(dev_priv)->num_pipes == 0)
+ if (NUM_PIPES(dev_priv) == 0)
return NULL;
error = kzalloc(sizeof(*error), GFP_ATOMIC);
@@ -15485,7 +15484,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv)
}
/* Note: this does not include DSI transcoders. */
- error->num_transcoders = DEVICE_INFO(dev_priv)->num_pipes;
+ error->num_transcoders = NUM_PIPES(dev_priv);
if (HAS_DDI(dev_priv))
error->num_transcoders++; /* Account for eDP. */
@@ -15524,7 +15523,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
if (!error)
return;
- err_printf(m, "Num Pipes: %d\n", DEVICE_INFO(dev_priv)->num_pipes);
+ err_printf(m, "Num Pipes: %d\n", NUM_PIPES(dev_priv));
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
err_printf(m, "PWR_WELL_CTL2: %08x\n",
error->power_well_driver);
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 440c1e624256..f3ecdcb3b32f 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -85,7 +85,7 @@ enum i9xx_plane_id {
};
#define plane_name(p) ((p) + 'A')
-#define sprite_name(p, s) ((p) * DEVICE_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
+#define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
/*
* Per-pipe plane identifier.
@@ -200,20 +200,20 @@ struct intel_link_m_n {
};
#define for_each_pipe(__dev_priv, __p) \
- for ((__p) = 0; (__p) < DEVICE_INFO(__dev_priv)->num_pipes; (__p)++)
+ for ((__p) = 0; (__p) < NUM_PIPES(__dev_priv); (__p)++)
#define for_each_pipe_masked(__dev_priv, __p, __mask) \
- for ((__p) = 0; (__p) < DEVICE_INFO(__dev_priv)->num_pipes; (__p)++) \
+ for ((__p) = 0; (__p) < NUM_PIPES(__dev_priv); (__p)++) \
for_each_if((__mask) & BIT(__p))
#define for_each_universal_plane(__dev_priv, __pipe, __p) \
for ((__p) = 0; \
- (__p) < DEVICE_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
+ (__p) < RUNTIME_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
(__p)++)
#define for_each_sprite(__dev_priv, __p, __s) \
for ((__s) = 0; \
- (__s) < DEVICE_INFO(__dev_priv)->num_sprites[(__p)]; \
+ (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
(__s)++)
#define for_each_port_masked(__port, __ports_mask) \
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 45c82f9e84b8..122422fdae4b 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1135,7 +1135,7 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
* Only consider slices where one, and only one, subslice has 7
* EUs
*/
- if (!is_power_of_2(DEVICE_INFO(dev_priv)->sseu.subslice_7eu[i]))
+ if (!is_power_of_2(INTEL_SSEU(dev_priv)->subslice_7eu[i]))
continue;
/*
@@ -1144,7 +1144,7 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
*
* -> 0 <= ss <= 3;
*/
- ss = ffs(DEVICE_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
+ ss = ffs(INTEL_SSEU(dev_priv)->subslice_7eu[i]) - 1;
vals[i] = 3 - ss;
}
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 0b89cc6fea67..44bd80c1a790 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -664,7 +664,7 @@ int intel_fbdev_init(struct drm_device *dev)
struct intel_fbdev *ifbdev;
int ret;
- if (WARN_ON(DEVICE_INFO(dev_priv)->num_pipes == 0))
+ if (WARN_ON(NUM_PIPES(dev_priv) == 0))
return -ENODEV;
ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/intel_lpe_audio.c b/drivers/gpu/drm/i915/intel_lpe_audio.c
index c85d7ff00096..7d4e44d50029 100644
--- a/drivers/gpu/drm/i915/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/intel_lpe_audio.c
@@ -110,7 +110,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
pinfo.size_data = sizeof(*pdata);
pinfo.dma_mask = DMA_BIT_MASK(32);
- pdata->num_pipes = DEVICE_INFO(dev_priv)->num_pipes;
+ pdata->num_pipes = NUM_PIPES(dev_priv);
pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */
pdata->port[0].pipe = -1;
pdata->port[1].pipe = -1;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cc26b3f7a0cf..ca5ba7502f04 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2120,24 +2120,24 @@ make_rpcs(struct drm_i915_private *dev_priv)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (DEVICE_INFO(dev_priv)->sseu.has_slice_pg) {
+ if (INTEL_SSEU(dev_priv)->has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
- rpcs |= hweight8(DEVICE_INFO(dev_priv)->sseu.slice_mask) <<
+ rpcs |= hweight8(INTEL_SSEU(dev_priv)->slice_mask) <<
GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (DEVICE_INFO(dev_priv)->sseu.has_subslice_pg) {
+ if (INTEL_SSEU(dev_priv)->has_subslice_pg) {
rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
- rpcs |= hweight8(DEVICE_INFO(dev_priv)->sseu.subslice_mask) <<
+ rpcs |= hweight8(INTEL_SSEU(dev_priv)->subslice_mask) <<
GEN8_RPCS_SS_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (DEVICE_INFO(dev_priv)->sseu.has_eu_pg) {
- rpcs |= DEVICE_INFO(dev_priv)->sseu.eu_per_subslice <<
+ if (INTEL_SSEU(dev_priv)->has_eu_pg) {
+ rpcs |= INTEL_SSEU(dev_priv)->eu_per_subslice <<
GEN8_RPCS_EU_MIN_SHIFT;
- rpcs |= DEVICE_INFO(dev_priv)->sseu.eu_per_subslice <<
+ rpcs |= INTEL_SSEU(dev_priv)->eu_per_subslice <<
GEN8_RPCS_EU_MAX_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 5c40bfb365fe..1d2363b26364 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -42,7 +42,7 @@ static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
struct drm_i915_private *dev_priv = info->dev_priv;
struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
- if (info->pipe >= DEVICE_INFO(dev_priv)->num_pipes)
+ if (info->pipe >= NUM_PIPES(dev_priv))
return -ENODEV;
spin_lock_irq(&pipe_crc->lock);
@@ -778,7 +778,7 @@ static int display_crc_ctl_parse_pipe(struct drm_i915_private *dev_priv,
{
const char name = buf[0];
- if (name < 'A' || name >= pipe_name(DEVICE_INFO(dev_priv)->num_pipes))
+ if (name < 'A' || name >= pipe_name(NUM_PIPES(dev_priv)))
return -EINVAL;
*pipe = name - 'A';
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 86a771e49f72..d2f677dbbefd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1897,8 +1897,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
for (level = 0; level < wm_state->num_levels; level++) {
const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
- const int sr_fifo_size =
- DEVICE_INFO(dev_priv)->num_pipes * 512 - 1;
+ const int sr_fifo_size = NUM_PIPES(dev_priv) * 512 - 1;
if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
break;
@@ -2631,7 +2630,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
/* HSW allows LP1+ watermarks even with multiple pipes */
if (level == 0 || config->num_pipes_active > 1) {
- fifo_size /= DEVICE_INFO(dev_priv)->num_pipes;
+ fifo_size /= NUM_PIPES(dev_priv);
/*
* For some reason the non self refresh
@@ -6980,7 +6979,7 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
- switch (DEVICE_INFO(dev_priv)->sseu.eu_total) {
+ switch (INTEL_SSEU(dev_priv)->eu_total) {
case 8:
/* (2 * 4) config */
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index e31fffcbb305..29390aa39262 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -85,12 +85,10 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
#define I915_MAX_SUBSLICES 3
#define instdone_slice_mask(dev_priv__) \
- (INTEL_GEN(dev_priv__) == 7 ? \
- 1 : DEVICE_INFO(dev_priv__)->sseu.slice_mask)
+ (INTEL_GEN(dev_priv__) == 7 ? 1 : INTEL_SSEU(dev_priv__)->slice_mask)
#define instdone_subslice_mask(dev_priv__) \
- (INTEL_GEN(dev_priv__) == 7 ? \
- 1 : DEVICE_INFO(dev_priv__)->sseu.subslice_mask)
+ (INTEL_GEN(dev_priv__) == 7 ? 1 : INTEL_SSEU(dev_priv__)->subslice_mask)
#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
for ((slice__) = 0, (subslice__) = 0; \
--
2.16.1
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