Regards
Shashank
On 2/6/2018 6:28 PM, Vidya Srinivas wrote:
If the fb format is YUV, enable the plane CSC mode bits
for the conversion.
Signed-off-by: Vidya Srinivas <vidya.srinivas@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_display.c | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 18be7be..f813406 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6426,6 +6426,12 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
+#define PLANE_COLOR_CSC_MASK (0x7 << 17)
The bit definition should be aligned to previous definition, with once
space offset. Applies to all bits.
+#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17)
+#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17)
+#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17)
#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13)
#define PLANE_COLOR_ALPHA_MASK (0x3 << 4)
#define PLANE_COLOR_ALPHA_DISABLE (0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b4a5e05..d34adda 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3577,6 +3577,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
+ if (intel_format_is_yuv(fb->format->format))
+ plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
I guess this is with the assumption that both the gamut are in 709
format, need not to be. But this should be taken care by plane CSC
property patch, so ok for now.
- Shashank
return plane_color_ctl;
}
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