Regards
Shashank
On 2/6/2018 6:28 PM, Vidya Srinivas wrote:
From: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx>
DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
this line / statement can be more clear, "DDB value to be as high as
level below " what is level below ? are we talking about C state level
or DDB level ?
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 07fc084..d9801bf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4531,6 +4531,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint16_t ddb_allocation,
int level,
const struct skl_wm_params *wp,
+ const struct skl_wm_level *result_prev,
struct skl_wm_level *result /* out */)
{
const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4598,6 +4599,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
} else {
res_blocks++;
}
+
+ /*
+ * Make sure result blocks for higher latency levels are atleast
+ * as high as level below.
what is level below ? latency level or you mean "one level below the
current level" ? Please reformat this comment.
+ * Assumption in DDB algorithm optimization for special cases.
+ * Also covers Display WA #1125 for RC.
+ */
+ if (result_prev->plane_res_b > res_blocks)
+ res_blocks = result_prev->plane_res_b;
}
if (INTEL_GEN(dev_priv) >= 11) {
@@ -4680,6 +4690,13 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
&wm->wm[level];
+ struct skl_wm_level *result_prev;
+
+ if (level)
+ result_prev = plane_num ? &wm->uv_wm[level - 1] :
+ &wm->wm[level - 1];
+ else
+ result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0];
ret = skl_compute_plane_wm(dev_priv,
cstate,
@@ -4687,6 +4704,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
ddb_blocks,
level,
wm_params,
+ result_prev,
result);
if (ret)
return ret;
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