---
tests/Makefile.sources | 1 +
tests/gem_exec_load.c | 176 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 177 insertions(+)
create mode 100644 tests/gem_exec_load.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 870c90935..8b5a18680 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -79,6 +79,7 @@ TESTS_progs = \
gem_exec_gttfill \
gem_exec_latency \
gem_exec_lut_handle \
+ gem_exec_load \
gem_exec_nop \
gem_exec_parallel \
gem_exec_params \
diff --git a/tests/gem_exec_load.c b/tests/gem_exec_load.c
new file mode 100644
index 000000000..ba88466a9
--- /dev/null
+++ b/tests/gem_exec_load.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "igt_rand.h"
+#include "igt_sysfs.h"
+
+IGT_TEST_DESCRIPTION("Apply a random load to each engine");
+
+static inline uint32_t randmax(uint32_t *state, uint32_t ep_ro)
+{
+ return (uint64_t)hars_petruska_f54_1_random(state) * ep_ro >> 32;
+}
+
+static void one(int fd, unsigned int engine, int scale, unsigned int timeout)
+{
+ uint32_t prng = engine;
+ igt_spin_t *spin[2] = {};
+ unsigned int max;
+ int sysfs;
+
+ sysfs = igt_sysfs_open(fd, NULL);
+
+ max = sysfs < 0 ? 1 : igt_sysfs_get_u32(sysfs, "gt_max_freq_mhz");
+
+ igt_until_timeout(timeout) {
+ /*
+ * For every second, we randomly assign a desire % busyness
+ * and the frequency with which to submit a batch, defining
+ * a pulse-width modulation (pwm).
+ */
+ unsigned int pwm = randmax(&prng, 1000);
+ unsigned int load = randmax(&prng, pwm / scale);
+ const unsigned int interval = 1e6 / pwm;
+ unsigned int cur =
+ max > 1 ? igt_sysfs_get_u32(sysfs, "gt_cur_freq_mhz") : 1;
+
+ while (pwm--) {
+ if (randmax(&prng, pwm * cur) <= load * max) {
+ spin[1] = __igt_spin_batch_new(fd, 0, engine, 0);
+ load--;
+ }
+ igt_spin_batch_free(fd, spin[0]);
+ spin[0] = spin[1];
+ spin[1] = NULL;
+
+ usleep(interval);
+ }
+ }
+ igt_spin_batch_free(fd, spin[0]);
+
+ close(sysfs);
+}
+
+static void all(int fd, unsigned int timeout)
+{
+ unsigned int engines[16];
+ unsigned int nengine;
+ unsigned int engine;
+
+ nengine = 0;
+ for_each_engine(fd, engine)
+ engines[nengine++] = engine;
+ igt_require(nengine > 1);
+
+ for (unsigned int n = 0; n < nengine; n++)
+ igt_fork(child, 1)
+ one(fd, engines[n], nengine/2, timeout);
+ igt_waitchildren();
+}
+
+static void pulse(int fd, unsigned int timeout)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ struct drm_i915_gem_exec_object2 obj[2] = {
+ { .flags = EXEC_OBJECT_WRITE },
+ };
+ unsigned int engines[16];
+ unsigned int nengine;
+ unsigned int engine;
+
+ nengine = 0;
+ for_each_engine(fd, engine) {
+ if (engine == 0)
+ continue;
+
+ engines[nengine++] = engine;
+ }
+ igt_require(nengine);
+
+ obj[1].handle = gem_create(fd, 4096);
+ gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
+
+ igt_until_timeout(timeout) {
+ for (unsigned int s = 0; s < nengine; s++) {
+ int64_t boost = 10e6; /* 10ms, long enough to sleep */
+ igt_spin_t *spin;
+
+ spin = __igt_spin_batch_new(fd, 0, engines[s], 0);
+ obj[0].handle = spin->handle;
+ for (unsigned int n = 0; n < nengine; n++) {
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 2,
+ .buffers_ptr = to_user_pointer(obj),
+ .flags = engines[n],
+ };
+ for (unsigned int repeat = 0;
+ repeat < 64;
+ repeat++)
+ gem_execbuf(fd, &eb);
+ }
+ gem_wait(fd, spin->handle, &boost);
+ igt_spin_batch_free(fd, spin);
+
+ gem_quiescent_gpu(fd);
+ }
+ }
+
+ gem_close(fd, obj[1].handle);
+}
+
+igt_main
+{
+ const struct intel_execution_engine *e;
+ int fd = -1;
+
+ igt_skip_on_simulation();
+
+ igt_fixture {
+ fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(fd);
+ igt_fork_hang_detector(fd);
+ }
+
+ for (e = intel_execution_engines; e->name; e++) {
+ /* default exec-id is purely symbolic */
+ if (e->exec_id == 0)
+ continue;
+
+ igt_subtest_f("%s", e->name) {
+ gem_require_ring(fd, e->exec_id | e->flags);
+ one(fd, e->exec_id | e->flags, 1, 150);
+ }
+ }
+
+ igt_subtest("all")
+ all(fd, 900);
+
+ igt_subtest("pulse")
+ pulse(fd, 900);
+
+ igt_fixture {
+ igt_stop_hang_detector();
+ close(fd);
+ }
+}
