On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> i965 and g4x still have the pipe select bits in the plane control
> registers, they're just hardcoded to select a specific pipe. However
> plane C on i965 can still move between the pipes, thus we should
> program the pipe select bits on i965 if we want to expose plane C
> some day.
>
> Since there is no harm in programming the bits on any plane on
> i965/g4x let's just always set them. This will also make our
> pre-computed register value match what the hardware register
> would read, should we want to cross check the two.
>
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index cccc1126f1d5..6ffc1d088d7a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3163,7 +3163,7 @@ static u32 i9xx_plane_ctl(const struct
> intel_crtc_state *crtc_state,
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
>
> - if (INTEL_GEN(dev_priv) < 4)
> + if (INTEL_GEN(dev_priv) < 5)
> dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
>
> switch (fb->format->format) {
--
Mika Kahola - Intel OTC
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