On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> G4x cursor control registers still allow us to write to the pipe
> select
> bits even though cursors are supposed to be fixed to a specific pipe.
> Bspec tells us that we should only ever write 0 to these bits. Let's
> follow that recommendation. On ilk+ the bits become hardwired to 0.
>
> Also looks like ICL repurposes these bits for some other use, so
> we had better stop setting them to bogus values there.
>
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index af659d25943b..cccc1126f1d5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9532,7 +9532,8 @@ static u32 i9xx_cursor_ctl(const struct
> intel_crtc_state *crtc_state,
> if (HAS_DDI(dev_priv))
> cntl |= CURSOR_PIPE_CSC_ENABLE;
>
> - cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
> + if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
> + cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
>
> switch (plane_state->base.crtc_w) {
> case 64:
--
Mika Kahola - Intel OTC
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