These two functions are very similar so simplify things by removing the
duplication.
Add a seperate sleeping poll timeout parameter, useful for longer polls
like the CDCLK change on BXT/GLK. The next patch will take that into use.
While at it document snb_pcode_request() and clean up a bit the
error/debug prints. Other than that no functional changes.
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 10 ++--
drivers/gpu/drm/i915/intel_cdclk.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 97 ++++++++++++++------------------------
3 files changed, 44 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5e293be4e51d..1e9911f66339 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3722,11 +3722,13 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv);
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
struct intel_display_error_state *error);
-int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
-int snb_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 val,
- int timeout_us);
+int snb_pcode_request(struct drm_i915_private *dev_priv, u32 mbox,
+ u32 send_val, u32 *recv_val,
+ int fast_timeout_us, int slow_timeout_ms);
+#define sandybridge_pcode_read(dev_priv, mbox, val) \
+ snb_pcode_request(dev_priv, mbox, *val, val, 500, 0)
#define sandybridge_pcode_write(dev_priv, mbox, val) \
- snb_pcode_request(dev_priv, mbox, val, 500)
+ snb_pcode_request(dev_priv, mbox, val, NULL, 500, 0)
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 5057336c40ba..8d06a6f66f29 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1377,7 +1377,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
*/
mutex_lock(&dev_priv->pcu_lock);
ret = snb_pcode_request(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
- 0x80000000, 2000);
+ 0x80000000, NULL, 2000, 0);
mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
@@ -1415,7 +1415,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* the next PCODE request based on BSpec.
*/
ret = snb_pcode_request(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
- cdclk_state->voltage_level, 2000);
+ cdclk_state->voltage_level, NULL, 2000, 0);
mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f6f4dbacb9af..5a6e5dcb6ff8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9123,7 +9123,29 @@ static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
}
}
-int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
+/**
+ * snb_pcode_request - send PCODE request
+ * @dev_priv: device private
+ * @mbox: PCODE mailbox ID the request is targeted for
+ * @send_val: request-ID or data to send
+ * @reply_val: buffer to store the reply in
+ * @fast_timeout_us: timeout for the request completion atomic wait
+ * @slow_timeout_ms: timeout for the request completion sleeping wait
+ *
+ * Send a PCODE request with @send_val as the request-ID or data as parameter.
+ * Wait @fast_timeout_us atomically then @slow_timeout_ms with sleeping wait
+ * for the request completion then if @reply_val is not NULL store the reply
+ * returned by PCODE in it.
+ *
+ * Returns
+ * - 0 on success
+ * - %-EAGAIN if PCODE is still busy with the previous request
+ * - %-ETIMEDOUT in case of a timeout
+ * - <0 in case of some other error as reported by PCODE
+ */
+int snb_pcode_request(struct drm_i915_private *dev_priv, u32 mbox,
+ u32 send_val, u32 *recv_val,
+ int fast_timeout_us, int slow_timeout_ms)
{
int status;
@@ -9133,26 +9155,27 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
* use te fw I915_READ variants to reduce the amount of work
* required when reading/writing.
*/
-
if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
- DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n",
- mbox, __builtin_return_address(0));
+ DRM_DEBUG_DRIVER("warning: pcode not ready for request 0x%08x to mbox 0x%x for %ps\n",
+ send_val, mbox, __builtin_return_address(0));
return -EAGAIN;
}
- I915_WRITE_FW(GEN6_PCODE_DATA, *val);
+ I915_WRITE_FW(GEN6_PCODE_DATA, send_val);
I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
if (__intel_wait_for_register_fw(dev_priv,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
- 500, 0, NULL)) {
- DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
- mbox, __builtin_return_address(0));
+ fast_timeout_us, slow_timeout_ms,
+ NULL)) {
+ DRM_ERROR("timeout waiting for pcode request 0x%08x to mbox 0x%x to finish for %ps\n",
+ send_val, mbox, __builtin_return_address(0));
return -ETIMEDOUT;
}
- *val = I915_READ_FW(GEN6_PCODE_DATA);
+ if (recv_val)
+ *recv_val = I915_READ_FW(GEN6_PCODE_DATA);
I915_WRITE_FW(GEN6_PCODE_DATA, 0);
if (INTEL_GEN(dev_priv) > 6)
@@ -9160,59 +9183,11 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
else
status = gen6_check_mailbox_status(dev_priv);
- if (status) {
- DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
- mbox, __builtin_return_address(0), status);
- return status;
- }
+ if (status)
+ DRM_DEBUG_DRIVER("warning: pcode request %08x to mbox 0x%x failed for %ps: %d\n",
+ send_val, mbox, __builtin_return_address(0), status);
- return 0;
-}
-
-int snb_pcode_request(struct drm_i915_private *dev_priv,
- u32 mbox, u32 val, int timeout_us)
-{
- int status;
-
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
-
- /* GEN6_PCODE_* are outside of the forcewake domain, we can
- * use te fw I915_READ variants to reduce the amount of work
- * required when reading/writing.
- */
-
- if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
- DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n",
- val, mbox, __builtin_return_address(0));
- return -EAGAIN;
- }
-
- I915_WRITE_FW(GEN6_PCODE_DATA, val);
- I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
- I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
-
- if (__intel_wait_for_register_fw(dev_priv,
- GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
- timeout_us, 0, NULL)) {
- DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
- val, mbox, __builtin_return_address(0));
- return -ETIMEDOUT;
- }
-
- I915_WRITE_FW(GEN6_PCODE_DATA, 0);
-
- if (INTEL_GEN(dev_priv) > 6)
- status = gen7_check_mailbox_status(dev_priv);
- else
- status = gen6_check_mailbox_status(dev_priv);
-
- if (status) {
- DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
- val, mbox, __builtin_return_address(0), status);
- return status;
- }
-
- return 0;
+ return status;
}
static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
--
2.13.2
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