On 2018-01-22 05:43 PM, Manasi Navare wrote: > Existing helpers add support upto HBR2. This patch > adds support for HBR3 rate (8.1 Gbps) introduced as > part of DP 1.4 specification. > > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> > Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx > Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx> Both patches look right according to DP 1.4 spec. Series is Reviewed-by: Harry Wentland <harry.wentland@xxxxxxx> Harry > --- > drivers/gpu/drm/drm_dp_helper.c | 4 ++++ > drivers/gpu/drm/drm_dp_mst_topology.c | 3 +++ > include/drm/drm_dp_helper.h | 1 + > 3 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index adf79be..ffe14ec 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -146,6 +146,8 @@ u8 drm_dp_link_rate_to_bw_code(int link_rate) > return DP_LINK_BW_2_7; > case 540000: > return DP_LINK_BW_5_4; > + case 810000: > + return DP_LINK_BW_8_1; > } > } > EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); > @@ -161,6 +163,8 @@ int drm_dp_bw_code_to_link_rate(u8 link_bw) > return 270000; > case DP_LINK_BW_5_4: > return 540000; > + case DP_LINK_BW_8_1: > + return 810000; > } > } > EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c > index 70dcfa5..36df7df 100644 > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > @@ -2087,6 +2087,9 @@ static bool drm_dp_get_vc_payload_bw(int dp_link_bw, > case DP_LINK_BW_5_4: > *out = 10 * dp_link_count; > break; > + case DP_LINK_BW_8_1: > + *out = 15 * dp_link_count; > + break; > } > return true; > } > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 9d3ce3b..c80fa92 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -334,6 +334,7 @@ > # define DP_LINK_BW_1_62 0x06 > # define DP_LINK_BW_2_7 0x0a > # define DP_LINK_BW_5_4 0x14 /* 1.2 */ > +# define DP_LINK_BW_8_1 0x1e /* 1.4 */ > > #define DP_LANE_COUNT_SET 0x101 > # define DP_LANE_COUNT_MASK 0x0f > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
