On Fri, 2018-01-19 at 16:05 -0800, Rodrigo Vivi wrote:
> On some Cannonlake SKUs we have a dedicated Aux for port F,
> that is only the full split between port A and port E.
>
> There is still no Aux E for Port E, as in previous platforms,
> because port_E still means shared lanes with port A.
>
> v2: Rebase.
> v3: Add couple missed PORT_F cases on intel_dp.
> v4: Rebase and fix commit message.
> v5: Squash Imre's "drm/i915: Add missing AUX_F power well string"
> v6: Rebase on top of display headers rework.
> v7: s/IS_CANNONLAKE/IS_CNL_WITH_PORT_F (DK)
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
> drivers/gpu/drm/i915/intel_display.h | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++
> 6 files changed, 36 insertions(+)
<snip>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 83b3f02d33b7..381c6758f3a6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1312,6 +1312,7 @@ enum i915_power_well_id {
> CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
> CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
> CNL_DISP_PW_AUX_D,
> + CNL_DISP_PW_AUX_F = 13,
Should be 12, status bit is 24 (= id*2) and request is 25 (= id*2 + 1)
>
> SKL_DISP_PW_1 = 14,
> SKL_DISP_PW_2,
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