On Thu, Jan 18, 2018 at 7:50 PM, C, Ramalingam <ramalingam.c@xxxxxxxxx> wrote: >> -----Original Message----- >> From: Sean Paul [mailto:seanpaul@xxxxxxxxxxxx] >> Sent: Friday, January 19, 2018 3:54 AM >> To: C, Ramalingam <ramalingam.c@xxxxxxxxx> >> Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; seanpaul@xxxxxxxxxxxx; >> daniel.vetter@xxxxxxxx; Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx>; Sharma, >> Shashank <shashank.sharma@xxxxxxxxx> >> Subject: Re: [PATCH 2/4] drm/i915: II stage HDCP auth for repeater only >> >> On Thu, Jan 18, 2018 at 11:18:06AM +0530, Ramalingam C wrote: >> > Second stage of HDCP authentication required only if the HDCP sink is >> > a repeater. >> > >> > This patch imposes above condition on second stage HDCP authentication. >> >> Hi Ram, >> This is already enforced in intel_hdcp_auth_downstream() > > I am not able to locate any check for repeater capability at start of downstream auth. > > I am not sure whether you are referring to number of downstream device count check. > That is valid after poll for ksv_fifo ready. We don't want to wait for 5Sec timeout in poll to detect the repeater cap. > > And since the caller is handy with the flag for repeater cap, it is best to decide on the call for downstream auth itself. > Thanks for clarifying, makes sense with the other patches in the set. Sean > Thanks > --Ram >> >> Thanks, >> Sean >> >> > >> > Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx> >> > --- >> > drivers/gpu/drm/i915/intel_hdcp.c | 5 ++++- >> > 1 file changed, 4 insertions(+), 1 deletion(-) >> > >> > diff --git a/drivers/gpu/drm/i915/intel_hdcp.c >> > b/drivers/gpu/drm/i915/intel_hdcp.c >> > index 6ce6559897a6..b48c72cd0906 100644 >> > --- a/drivers/gpu/drm/i915/intel_hdcp.c >> > +++ b/drivers/gpu/drm/i915/intel_hdcp.c >> > @@ -493,7 +493,10 @@ static int intel_hdcp_auth(struct intel_digital_port >> *intel_dig_port, >> > * on those as well. >> > */ >> > >> > - return intel_hdcp_auth_downstream(intel_dig_port, shim); >> > + if (repeater_present) >> > + return intel_hdcp_auth_downstream(intel_dig_port, shim); >> > + >> > + return 0; >> > } >> > >> > static >> > -- >> > 2.7.4 >> > >> >> -- >> Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
