On Wed, Jan 17, 2018 at 10:31:09AM +0200, Mika Kuoppala wrote: > Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > > > Quoting Mika Kuoppala (2018-01-16 15:21:16) > >> There is a suspicion that with aggressive upclocking, power rail > >> voltage fluctuations can disrupt c state transition, leading > >> to system hang. > >> > >> When upclocking with 4 cpu Baytrails, bring up cpus to c1 and then > >> go through bins gradually towards target frequency to give leeway > >> for hw. > >> > >> We go towards requested frequency on 1 millisecond intervals. For > >> each 1 millisecond, we increase the frequency by half of bins > >> that are in between current frequency and target. > > > > Either this is good for everyone or it is not. Doing more punit accesses > > seems counter productive though, and adds 8ms to the initial request? > > Wanted to see if it is not punit access in itself but voltage rampup. We > can forget this patch as atleast with these values as it didn't survive > night. I guess one big problem is that the GPU frequency is just one small part of the voltage equation. RC6 might play a bigger role since it could cause the voltage to alternate between low and high values rapidly. And the Vnn rail is shared by most devices on the soc, so even just limiting things to the GPU might not be entirely sufficient. And if there's some link between the number of cores and the instability then the Vcc rail(s) are perhaps also suspect. And for those I guess we would have to somehow throttle the CPU C and P state transitions. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
