Re: [PATCH v3 03/12] drm/i915/guc: Pass intel_guc struct parameter to GuC interrupts functions

Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx> · Fri, 5 Jan 2018 10:00:18 +0530

On 1/4/2018 10:01 PM, Michal Wajdeczko wrote:
On Thu, 04 Jan 2018 17:23:05 +0100, Chris Wilson 
<chris@xxxxxxxxxxxxxxxxxx> wrote:

Quoting Sagar Arun Kamble (2018-01-04 16:21:45)
GuC interrupts handling functions are GuC specific functions hence 
update
the parameter from dev_priv to intel_guc struct.

v2-v3: Rebase.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
Cc: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
---
 drivers/gpu/drm/i915/i915_irq.c      |  2 +-
 drivers/gpu/drm/i915/intel_guc.c     | 22 +++++++++++++++-------
 drivers/gpu/drm/i915/intel_guc.h     |  8 ++++----
 drivers/gpu/drm/i915/intel_guc_log.c |  8 +++-----
 drivers/gpu/drm/i915/intel_uc.c      |  8 ++++----
 5 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c 
b/drivers/gpu/drm/i915/i915_irq.c
index 3f4eff9..a1ae057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1447,7 +1447,7 @@ static void gen8_gt_irq_handler(struct 
drm_i915_private *dev_priv,
                gen6_rps_irq_handler(dev_priv, gt_iir[2]);

        if (gt_iir[2] & dev_priv->pm_guc_events)
-               intel_guc_irq_handler(dev_priv, gt_iir[2]);
+               intel_guc_irq_handler(&dev_priv->guc, gt_iir[2]);
 }

 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
diff --git a/drivers/gpu/drm/i915/intel_guc.c 
b/drivers/gpu/drm/i915/intel_guc.c
index e95ff2d..14bf508d 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -400,7 +400,7 @@ int intel_guc_suspend(struct drm_i915_private 
*dev_priv)
        if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
                return 0;

-       intel_disable_guc_interrupts(dev_priv);
+       intel_disable_guc_interrupts(guc);

        data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
        /* any value greater than GUC_POWER_D0 */
@@ -446,7 +446,7 @@ int intel_guc_resume(struct drm_i915_private 
*dev_priv)
                return 0;

        if (i915_modparams.guc_log_level >= 0)
-               intel_enable_guc_interrupts(dev_priv);
+               intel_enable_guc_interrupts(guc);

        data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
        data[1] = GUC_POWER_D0;
@@ -508,15 +508,19 @@ u32 intel_guc_wopcm_size(struct 
drm_i915_private *dev_priv)
        return wopcm_size;
 }

-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_reset_guc_interrupts(struct intel_guc *guc)
 {
+       struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
        spin_lock_irq(&dev_priv->irq_lock);
        gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
        spin_unlock_irq(&dev_priv->irq_lock);
 }

-void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_enable_guc_interrupts(struct intel_guc *guc)
 {
+       struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
        spin_lock_irq(&dev_priv->irq_lock);
        if (!dev_priv->guc.interrupts_enabled) {
                WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
@@ -527,8 +531,10 @@ void intel_enable_guc_interrupts(struct 
drm_i915_private *dev_priv)
        spin_unlock_irq(&dev_priv->irq_lock);
 }

-void intel_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void intel_disable_guc_interrupts(struct intel_guc *guc)
 {
+       struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
        spin_lock_irq(&dev_priv->irq_lock);
        dev_priv->guc.interrupts_enabled = false;

@@ -537,11 +543,13 @@ void intel_disable_guc_interrupts(struct 
drm_i915_private *dev_priv)
        spin_unlock_irq(&dev_priv->irq_lock);
        synchronize_irq(dev_priv->drm.irq);

-       intel_reset_guc_interrupts(dev_priv);
+       intel_reset_guc_interrupts(guc);
 }

-void intel_guc_irq_handler(struct drm_i915_private *dev_priv, u32 
gt_iir)
+void intel_guc_irq_handler(struct intel_guc *guc, u32 gt_iir)
 {
+       struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
        if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
                /* Sample the log buffer flush related bits & clear 
them out now
                 * itself from the message identity register to 
minimize the
diff --git a/drivers/gpu/drm/i915/intel_guc.h 
b/drivers/gpu/drm/i915/intel_guc.h
index c37d34d..49f33b9 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -131,9 +131,9 @@ static inline u32 guc_ggtt_offset(struct 
i915_vma *vma)
 int intel_guc_resume(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 
size);
 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
-void intel_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void intel_enable_guc_interrupts(struct drm_i915_private *dev_priv);
-void intel_disable_guc_interrupts(struct drm_i915_private *dev_priv);
-void intel_guc_irq_handler(struct drm_i915_private *dev_priv, u32 
pm_iir);
+void intel_reset_guc_interrupts(struct intel_guc *guc);
+void intel_enable_guc_interrupts(struct intel_guc *guc);
+void intel_disable_guc_interrupts(struct intel_guc *guc);
+void intel_guc_irq_handler(struct intel_guc *guc, u32 pm_iir);

You should also consider s/intel_verb_guc/intel_guc_verb/ since we are
now passing intel_guc as the object.

And additionally also consider squashing this patch with 02/12 (and maybe
01/12 as well) to avoid changing the same lines twice
Sure. Will do these changes. Thanks Michal, Chris.

Michal


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