On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote: > On some Cannonlake SKUs we have a dedicated Aux for port F, > that is only the full split between port A and port E. > > There is still no Aux E for Port E, as in previous platforms, > because port_E still means shared lanes with port A. > > v2: Rebase. > v3: Add couple missed PORT_F cases on intel_dp. > v4: Rebase and fix commit message. > v5: Squash Imre's "drm/i915: Add missing AUX_F power well string" > v6: Rebase on top of display headers rework. > > Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> > Cc: Imre Deak <imre.deak@xxxxxxxxx> > Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_irq.c | 6 ++++++ > drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++ > drivers/gpu/drm/i915/intel_display.h | 1 + > drivers/gpu/drm/i915/intel_dp.c | 8 ++++++++ > drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++++++++++ > 6 files changed, 36 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index caebd5825279..53e401c792d0 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1255,6 +1255,7 @@ enum modeset_restore { > #define DP_AUX_B 0x10 > #define DP_AUX_C 0x20 > #define DP_AUX_D 0x30 > +#define DP_AUX_F 0x50 > > #define DDC_PIN_B 0x05 > #define DDC_PIN_C 0x04 > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 3517c6548e2c..8b8df5b8b8a7 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2579,6 +2579,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > GEN9_AUX_CHANNEL_C | > GEN9_AUX_CHANNEL_D; > > + if (IS_CANNONLAKE(dev_priv)) > + tmp_mask |= CNL_AUX_CHANNEL_F; Do we need to care about this if the SKU does not have the port? The interrupt status bits are checked only if a platform has the corresponding port. I think CNL SKU's with/without port F should be treated similarly. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx