Quoting Tvrtko Ursulin (2017-12-18 12:32:37)
>
> On 18/12/2017 12:17, Chris Wilson wrote:
> > A useful bit of information for inspecting GPU stalls from
> > intel_engine_dump() are the error registers, IPEIR and IPEHR.
> >
> > v2: Fixup gen changes in register offsets (Tvrtko)
> > v3: Old FADDR location as well
> >
> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_engine_cs.c | 20 ++++++++++++++++++++
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 510e0bc3a377..257b03a67e1c 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1757,6 +1757,26 @@ void intel_engine_dump(struct intel_engine_cs *engine,
> > addr = intel_engine_get_last_batch_head(engine);
> > drm_printf(m, " BBADDR: 0x%08x_%08x\n",
> > upper_32_bits(addr), lower_32_bits(addr));
> > + if (INTEL_GEN(dev_priv) >= 4) {
> > + if (INTEL_GEN(dev_priv) >= 8) {
> > + addr = I915_READ(RING_DMA_FADD_UDW(engine->mmio_base));
> > + addr <<= 32;
> > + }
> > + addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
>
> |=, or better reverse order to avoid having to init addr.
|= otherwise it's back to the ugly (u64) << 32;
Pick your poison. Or maybe if I started paying attention we wouldn't
need to be going round in some many circles.
-Chris
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