Quoting Joonas Lahtinen (2017-12-11 10:55:40)
> On Fri, 2017-12-08 at 21:46 +0000, Chris Wilson wrote:
> > Before accessing the GGTT we must flush the PTE writes and make them
> > visible to the chipset, or else the indirect access may end up in the
> > wrong page. In commit 3497971a71d8 ("agp/intel: Flush chipset writes
> > after updating a single PTE"), we noticed corruption of the uploads for
> > pwrite and for capturing GPU error states, but it was presumed that the
> > explicit calls to intel_gtt_chipset_flush() were sufficient for the
> > execbuffer path. However, we have not been flushing the chipset between
> > the PTE writes and access via the GTT itself.
> >
> > For simplicity, do the flush after any PTE update rather than try and
> > batch the flushes on a just-in-time basis.
> >
> > References: 3497971a71d8 ("agp/intel: Flush chipset writes after updating a single PTE")
> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> > Cc: drm-intel-fixes@xxxxxxxxxxxxxxxxxxxxx
>
> I don't think this is being used so much anymore? (+ Jani for this)
>
> Why not Cc: stable? My DIM says # v4.9+
I don't use stable@ anymore since Greg doesn't like our patches and
would much prefer to pick randomly instead. /slightly-s
So I leave that management to you guys.
-Chris
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