Em Seg, 2017-12-04 às 15:50 -0200, Paulo Zanoni escreveu:
> Em Seg, 2017-11-13 às 23:34 +0000, Lionel Landwerlin escreveu:
> > We apply this logic to Gen9 as well. We didn't notice this issue as
> > most part we've encountered so far only use the crystal as source
> > for
> > their timestamp registers.
> >
> > Fixes: dab9178333 ("drm/i915: expose command stream timestamp
> > frequency to userspace")
> > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx>
>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
I also merged this since I need it.
Patch 3 still needs a check from the people who were reviewing its
previous versions.
>
> > ---
> > drivers/gpu/drm/i915/intel_device_info.c | 16 ++++++++--------
> > 1 file changed, 8 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index f3e4940fed49..039f8ec7ad27 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -413,15 +413,15 @@ static u32 read_timestamp_frequency(struct
> > drm_i915_private *dev_priv)
> > freq = f24_mhz;
> > break;
> > }
> > - }
> >
> > - /* Now figure out how the command stream's
> > timestamp
> > register
> > - * increments from this frequency (it might
> > increment only
> > - * every few clock cycle).
> > - */
> > - freq >>= 3 - ((rpm_config_reg &
> > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMET
> > ER
> > _MASK) >>
> > - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETE
> > R_
> > SHIFT);
> > + /* Now figure out how the command stream's
> > timestamp
> > + * register increments from this frequency
> > (it might
> > + * increment only every few clock cycle).
> > + */
> > + freq >>= 3 - ((rpm_config_reg &
> > + GEN10_RPM_CONFIG0_CTC_SHIFT
> > _P
> > ARAMETER_MASK) >>
> > + GEN10_RPM_CONFIG0_CTC_SHIFT_
> > PA
> > RAMETER_SHIFT);
> > + }
> >
> > return freq;
> > }
>
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